Embedded Processors (ARM Architecture) - Unit 1

Embedded Processors Unit-1 AR Gangajaliwale AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE ARM – 7 Architecture AR GANGAJALIWA...

Embedded Processors Unit-1 AR Gangajaliwale AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE ARM – 7 Architecture AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE ARM Core Diagram AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE  CPSR-SPSR Feature CPSR (Current SPSR (Saved Program Program Status Status Register) Register) Purpose Holds the current Saves a copy of the state of the CPSR during an processor, including exception or mode condition flags and switch, allowing control bits. restoration. Usage Reflects the real-time Used to restore the execution state, flags previous state of the (NZCV), and control processor after configurations. exception handling. Location A single global One SPSR exists per register accessible at exception mode (e.g., all times in ARM IRQ, FIQ, SVC, etc.). architecture. Number of Registers Only one CPSR exists Multiple SPSRs, one for the entire for each exception processor. AR GANGAJALIWALE mode. Access Directly accessible Accessible only in and modifiable during privileged modes and normal operation during exception using instructions like handling. MSR. Bits Controlled Includes condition Saves all CPSR bits, flags (NZCV), including flags, interrupt enables interrupts, and mode (IRQ/FIQ), and bits. processor mode bits. Modification Can be directly Automatically modified via updated during instructions or during exceptions and used exception entry. to restore CPSR when resuming. Role in Exception CPSR changes to SPSR stores the reflect the new state original CPSR state of the processor before the exception during an exception. occurred. Scope Global: represents the Local: specific to the overall state of the current exception processor. AR GANGAJALIWALE mode. Special Notes Crucial for real-time Ensures smooth AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE AR GANGAJALIWALE