Introduction to ARM Cortex M0+ Processor PDF

Introduction to ARM Cortex M0+ Processor Le Yang ([email protected]) Department of Electrical and Computer Engineering Office Hours: Link Building A510, Mondays 16:00 – 18:00 1 Where we’re going...

Introduction to ARM Cortex M0+ Processor Le Yang ([email protected]) Department of Electrical and Computer Engineering Office Hours: Link Building A510, Mondays 16:00 – 18:00 1 Where we’re going today ARM Cortex-M0+ processor STM320C071x8/xB MCUs ARM Cortex-M0+ instruction set 2 Microcontroller (MCU) Microcontroller = Microprocessor (MPU) + Memory + Peripherals Microcomputer = microcontroller on a single silicon chip Of which 99% are Code Memory Data Memory Memory Bus Analogue to Digital Clock Microprocessor Converter (ADC) Peripheral Bus Digital Digital PWM* Analogue In Out Out In 3 * PWM: Pulse Width Modulation  ARM Cortex-M0+ Processor (1) 32-bit MPU introduced in 2012 ARMv6-M architecture Two-stage pipeline Fetch + pre-decode, decode + execute Thumb instruction set architecture (ISA) Most instructions are 16-bit Von Neumann structure Shared pathway/bus for program and data Pathway/bus competition 4  ARM Cortex-M0+ Processor (2) Built-in interrupt controller Nested vector interrupt controller (NVIC) Interrupt prioritization and masking 4 programmable priority levels + NMI Low-power support 9.8 uW/MHz (90 nm semiconductor process) Sleep and deep sleep modes Wait for Input (WFI)/Wait for Event (WFE) Wake-up Interrupt Controller (WIC) Debug: JTAG/SWD 5 ARM and RISC ARM: Advanced RISC Machine First developed by Acorn Computers in the mid 80’s based on RISC concept originated at Stanford & Berkeley Now a separate company licensing ARM cores to STMicroelectronics, Texas Instruments, Atmel, Motorola … RISC vs. CISC RISC: Reduced Instruction Set Computer One instruction for one operation, executed within one clock cycle Larger code size but less complicated hardware (advantage) CISC: Complex Instruction Set Computer One instruction for multiple operations, run over several clock cycles Shorter code length but complex (control) hardware 6 Pioneers in RISC Computers 2022 Charles Stark Draper Prize for Engineering Conceptualization, prototyping and benchmarking in 1980s David Patterson, UC Berkeley John Hennessy, Stanford Commercialization Stephen Furber and Sophie Wilson, Acorn Computers Acorn/Advanced RISC machine (ARM) 7 https://www.nae.edu/266390/RISC-Chip-Innovators-Receive-the-2022-Charles-Stark-Draper-Prize-for-Engineering UC Inventor of RISC Embedded Processors David Jagger B.S. from UC, Computer Science, 1987 M.S. from UC, Computer Science, 1991 Thesis title: A performance study of the Acorn RISC machine Computer Scientist, ARM, 1992-2000 Designer of ARM7, ARM10 Inventor of Thumb architecture James Clerk Maxwell Medal from IEEE, 2019 8 https://www.canterbury.ac.nz/alumni/our-alumni/notable-alumni/david-jaggar/ Where we’re going today ARM Cortex-M0+ processor STM320C071x8/xB MCUs ARM Cortex-M0+ instruction set 9 STM32C071x8/xB MCU Architecture FLASH: 128 KB SRAM: 36 KB RCC: RESET & Clock Control CRC: Cyclic Redundancy Check EXTI: Extended Interrupt & Event Controller AHB: Advanced High-Performance Bus Better back-to-back access performance APB: Advanced Peripheral Bus Legacy bus 10 RM0490 Reference manual STM32C0 series advanced Arm®-based 32-bit MCUs.pdf STM32C071x8/xB MCUs Based on ARM Cortex-M0+ CPU STM32C071RBT6 STM32C071CB STM32C071KB STM32C071GBU6 Circles: modules relevant to this course Homework: find out the definition of each acronym in the diagram 11 Typical Application Scenario Program: Code + Data Central Processing Unit (CPU) ARM Cortex-M0+ processor LED: Lights Emitting Diode Semiconducter light source for signalling Piezo buzzer Audio signalling device to indicate button pressing (click, ring or beep) Optocoupler: light emitter + receiver Signal detection in electrical noise … 12 Where we’re going today ARM Cortex-M0+ processor STM320C071x8/xB MCUs ARM Cortex-M0+ instruction set 13 Example of Cortex-M0+ Instructions 56 16-bit instructions 6 32-bit instructions NOT for heavy-duty number-crunching tasks S: cause an instruction to update flags (Negative, Zero, Carry, oVerflow) Rd: result register Rn/Rm: First/second source register cc: conditional execution (EQ, NE, GT, LT, LE, …) 14 Cortex-M0+ Devices_Generic Users Guide.pdf Example Program in Assembly BEQ label ; Branch to label if previous operation results in equal status (Z = 1) ADD R0, R1, R2 ; Carry out R0 = R1 + R2 without affecting the flags What does the following code do? (refer to slide 18) CMP R0, #9 BLE label_LE ADD R1, R0, #55 B next label_LE ADD R1, R0, #48 next … 15 Supplementary Materials Fundamental data types ASCII table ARM licensing Evolution of ARM process architecture 16 Fundamental Data Types 17 ASCII Table American Standard Code for Information Interchange Numerical representation of characters Code 48 – 57 ‘0’ – ‘9’ Code 65 – 70 ‘A’ – ‘F’ Hint: hex numerical system has 16 symbols … 18 ARM Licensing (1) Licensee must follow ARM CPU architecture and instruction set But free to implement their own peripherals (I/O ports, ADCs, Timers, SPI…) Functional registers and their physical locations are not standardized Assembly language programs for ARM chip can be run on any ARM chip Assembly language programs for peripherals on one ARM chip may not be able to run on other ARM chips Two approaches for programming ARM chip peripherals Use propriety device library of functions from ARM chip vendor Write your own programs with customized interfaces 19 ARM Licensing (2) 20 Evolution of ARM Processor Architecture 21