COMP 1027 Computer Fundamentals Revision + Exam PDF

COMP-1027 Computer Fundamentals Lecture 11 Revision + Exam  Learning Outcomes REVIEW EXAMINE Everything we have EXAM Format LEARNED so far… COMP 1027 Revision + Exam 2 Lecture 1...

COMP-1027 Computer Fundamentals Lecture 11 Revision + Exam  Learning Outcomes REVIEW EXAMINE Everything we have EXAM Format LEARNED so far… COMP 1027 Revision + Exam 2 Lecture 1 Introduction + Evolution What is THAT??? ??? What is a “COMPUTER”? COMP 1027 Revision + Exam 4 Computer Components CPU Storage COMP 1027 Revision + Exam 5 Computer Properties Fast Accurate Properties Consistency General Purpose: different program → achieve different functionality Can it think? Invent? Is it intelligent? COMP 1027 Revision + Exam 6 Evolution & Generations of Computers https://humanswlord.files.wordpress.com/2014/01/moores-law-graph-gif.png COMP 1027 Revision + Exam 7 Abstraction L. Null, L. and J. Lobur, The essentials of computer organisation and architecture, Jones & Bartlett Publishers, 2003 (Fig. 1.3, P.26) COMP 1027 Revision + Exam 8 Overview HACK CPU Memory ALU Controls Registers Combinational Sequential Logic Logic Logic Gates Electronic Circuits COMP 1027 Revision + Exam 9 Lectures 2 Electronics to Logic Gates Boolean  Boolean Algebra: Basic Gates Boolean Product Boolean Sum x y X.y x y X+y x X’ 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 Boolean Expression COMP 1027 Revision + Exam 11 Universal Logic Gates L. Null, L. and J. Lobur, The essentials of computer organisation and architecture, Jones & Bartlett Publishers, 2003 COMP 1027 Revision + Exam 12  Example: “Majority Function” F(x,y,z) = x’yz + xy’z + xyz’ + xyz Boolean Expression 4: x’.y.z Boolean Expression 3: x.y’.z Boolean Expression 2: x.y.z’ Boolean Expression 1: x.y.z COMP 1027 Revision + Exam 13  Boolean Algebra: Identities Simply: 3a + 5a = ? 8a x y X.y x y X+y 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1 HW: Write the truth table for both sides of expressions L. Null, L. and J. Lobur, The essentials of computer organisation and architecture, Jones & Bartlett Publishers, 2003 (Fig. 1.3, P.26) COMP 1027 Revision + Exam 14 Lectures 3 Combinatorial Circuits  Numbering System (Number Representation) Decimal Numbers Count, from 1…to…10. COMP 1027 Revision + Exam 17  Binary Numbers Set of 2 numbers: {0, 1} WHAT Intuitive for Electronics (Switch: OFF/ON) Quick Question: What is the (decimal) value of 0101? 3 2 1 0 23 22 21 20 0 * 23 1 * 22 0 * 21 1 * 20 COMP 1027 Revision + Exam 18  Convert DECIMAL to BINARY Generic Algorithm: 1. Divide by the base (2). 2. Record result & remainder. 3. Divide the result, by the base (2). 4. Repeat (1-3) till result = 0. Binary=Sequence of reminders COMP 1027 Revision + Exam 19 More System COMP 1027 Revision + Exam 20 Negative Numbers S. Bagley, UNUK COMP 1027 Revision + Exam 21 Negative Numbers (Two’s Complement) 0 0000 1 0001 1111 -1 2 0010 1110 -2 Standard in all CPUs 3 0011 1101 -3 The codes of all positive numbers begin with a “0” 4 0100 1100 -4 The codes of all negative numbers begin with a “1” 5 0101 1011 -5 6 0110 1010 -6 7 0111 1001 -7 COMP 1027 Revision + Exam 22 Combinatorial Circuits  HALF Adder A B C (Carry) S (Sum) 0 0 0 0 S A⨁B AB’ + A’B 0 1 0 1 1 0 0 1 C A.B 1 1 1 0 A Sum ‘S’ Half Adder B Carry ‘C’ COMP 1027 Revision + Exam 24 FULL Adder INPUTS OUTPUTS A B CIN COUT S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 IMPORTANT 1 0 0 0 1 COUT is true only if any of the two inputs 1 0 1 1 0 out of the three are at logic 1 1 1 0 1 0 1 1 1 1 1 COMP 1027 Revision + Exam 25 n-bit FULL Adder (Chain of 1-bit Full Adders) Each adder’s Cout wired into Cin of the next nth bit of each input presented to the nth adder’s inputs A and B First adder’s carry input is 0 (usually) Last adder’s carry output tells if we’ve overflowed COMP 1027 Revision + Exam 26  Subtraction (Design Circuit) X-Y B D HALF ADDER X Y (Borrow) (Diff) 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Remind us with something? (similar circuit) HALF- Subtractor COMP 1027 Revision + Exam 27 Multiplexer (MUX) Choosing input Output Digitally tuning radio to choose a station a b sel out sel out 0 0 0 0 0 a 0 0 1 0 a 1 b 0 1 0 0 0 1 1 1 Mux out b 1 0 0 1 1 0 1 0 1 1 0 1 a sel out 1 1 1 1 b sel COMP 1027 Revision + Exam 28  Exercise (to discover…) a b s F 0 0 0 0 0 0 1 0 a 0 1 0 0 0 1 1 1 Mux out 1 0 0 1 b 1 0 1 0 1 1 0 1 sel 1 1 1 1 s F 0 a 1 b COMP 1027 Revision + Exam 29 Lectures 4 ALU  ALU controls [ALL] zx nx f no x x1 x2 x2&y2 0 AND16 x‘1 Out1 Out y Out1’ y1 16-bit x2+y2 y2 Full Adder y‘1 zy ny COMP 1027 Revision + Exam 31 ALU Controls S. Bagley, UNUK COMP 1027 Revision + Exam 32 ALU Controls (Also in Lab) COMP 1027 Revision + Exam 33 Lectures 5 Sequential Circuits SR Latch S R Qn Means 0 0 Qc No change 0 1 0 Reset to 0 1 0 1 Set to 1 1 1 !! Undefined!! L. Null, L. and J. Lobur, The essentials of computer organisation and architecture, Jones & Bartlett Publishers, 2003 COMP 1027 Revision + Exam 35  D (Solution 2: From SR) What did we lose here? DFF Remember its input. D-FlipFlop Stores input L. Null, L. and J. Lobur, The essentials of computer organisation and architecture, Jones & Bartlett Publishers, 2003 COMP 1027 Revision + Exam 36  4-bit Register n-bit Registers: n 1-bit registers, parallel, same “CLK signal”, same “load” S. Bagley - UNUK COMP 1027 Revision + Exam 37  RAM Ioad 8-byte RAM? In (8) Byte = 8 bits out (8) 8-byte → 8 x 8-bit Registers RAM address (?) Need to consider: 1. Only ONE register should be read at a time. [Read] 2. Only ONE register should be updated (Loaded) at a time. [Write] COMP 1027 Revision + Exam 38 RAM COMP 1027 Revision + Exam 39 Program Counter ? Holds the ”Address” of the next instruction to be executed Need to have: INC: Enable increment, to keep counting (the normal counter behaviour) RESET: to start from scratch. LOAD: to load a specific address, where execution need to start from (e.g. jump, function call,…) Register We can utilise chips we Increment (Inc). built before, though: MUX: to choose… COMP 1027 Revision + Exam 40 Program Counter COMP 1027 Revision + Exam 41 Lectures 6 Machine Code Machine Code Interface Between HW & SW Img: Techcrunch.com COMP 1027 Revision + Exam 43  The A-instruction: Addressing Modes Coding examples (Assembly): Data is part of the instruction Immediate: Value moved directly into Register A @17 // A = 17 Address is not part of the instruction, but taken Direct: from A @17 // A = 17 Data: RAM, at location address by A (contents) D = M // D = RAM Program: ROM, at location addressed by A (PC=A) @17 // A = 17 Indirect: See illustration, next JMP // fetch the instruction // stored in ROM Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, Chapter 4: Machine language. COMP 1027 Revision + Exam 44  Examples of Addressing Modes Address is part of instruction Immediate: No need to access memory Limited to 215 +ve numbers Value: fixed in code Address is in A. Direct: Limited to 215 locations Larger memory needed? Not enough! Instruction contains; Address of the data’s address Indirect: (no data, not its address, an address to its address) More memory access, to get address, then data More addresses & values: extra bit available COMP 1027 Revision + Exam 45  The C-instruction: FORMAT Symbolic: dest= comp; jump dest= comp; OR comp; OR comp; jump Example: Example: Example: @END; //A=Address of END D=D|M D|M //no save D|M; JGT // if>0 jump Binary: // to Address defined in A. Binary: 1111 0101 0100 0000 1111 0101 0101 0000 Binary: Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, Chapter 4: Machine language. 1111 0101 0100 0001 COMP 1027 Revision + Exam 46  Example: Add 1+…+100 (coloured) Hack assembly code: // Adds 1+...+100. // Adds 1+...+100. @i // i refers to some RAM location int i = 1; M=1 // i=1 int sum = 0; @sum // sum refers to some RAM location while (i 0 goto END @i Hack assembly convention: D=M // D = i @sum Variable: lower-case M=D+M // sum += i Labels: upper-case @i M=M+1 // i++ Commands: upper-case @LOOP 0;JMP // Got LOOP Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, (END) Chapter 4: Machine language. @END 0;JMP // Infinite loop COMP 1027 Revision + Exam 47 Lectures 7 Memory I/O & CPU Controls Hack Computer Architecture (Conceptual) Instruction Read memory Program (Chip: ROM32K) Read / Write Data Data Memory (Chip: Memory) I/O Mapped Read / Write [Screen/KBD] Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, Chapter 5 COMP 1027 Revision + Exam 49 Hack Computer (Computer) Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, Chapter 5 COMP 1027 Revision + Exam 50  Fetch-Execute Cycle Access the instruction (to be executed) Instructions Memory Access - Address in PC - Access ROM[PC] → Read instruction Fetch Decode instruction: A- or C- instruction If C-instruction → Decode the 3 parts: dest, comp, jump → execute… Decode COMP 1027 Revision + Exam 51  dest = com p; jum p com p dest jum p b i n ary: 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALU output Chip Diagram Includes most of C C the exec. Logic C D D Control logic is C C decode hinted. outM ALU C A Mux A C instruction A/M Mux M inM C writeM Need to A addressM define all C reset control logic A PC pc Nisan and Schocken, Elements of Computing Systems, MIT Press, www.nand2tetris.org, Chapter 5 COMP 1027 Revision + Exam 52 Lectures 8 Networks OSI Model - Layers All Application Away People Presentation Pizza Seem Session Sausage To Transport Throw Need Network Not Data Data Link Do Processing Physical Please COMP 1027 Revision + Exam 54 Compare… http://techdifferences.com/difference-between-tcp-ip-and-osi-model.html COMP 1027 Revision + Exam 55 IP Address (Classes) COMP 1027 Revision + Exam 56 Classless Inter-Domain Routing IPv4 → 4 billion - but running out. CIDR: Aimed to slow the rapid growth of routing tables, and slow IP address space exhaustion Allows a variable number of bits to be used to identify the network (not just a fixed multiple of 8-bits) Generally written as an IP address followed by the number of bits that represent the network, e.g. - 10.0.0.1/8, - 192.168.1.1/24, - 81.143.155.173/30 COMP 1027 Revision + Exam 57 LITTLE Endian Let us take the IP address; 32 bits, as an example: In Hex: MSB LSB 0x12 34 56 78 31-24 23-16 15-8 7-0 78 56 34 12 Byte 0 1 2 3 COMP 1027 Revision + Exam 58  BIG Endian Let us take the IP address; 32 bits, as an example: In Hex: MSB LSB 0x12 34 56 78 31-24 23-16 15-8 7-0 Network Standard 12 34 56 78 ( Big Endean ) Byte 0 1 2 3 COMP 1027 Revision + Exam 59 Lectures 9 Socket Programming Client - Server Example COMP 1027 Revision + Exam 61 Socket Programming (Server) CLIENT SIDE SERVER SIDE COMP 1027 Revision + Exam 62  Socket Programming (Together) socket() bind() socket() listen() connect() accept() CLIENT SIDE send() recv() SERVER SIDE Waiting for Client’s requests recv() send() Listening to Specific Port close() close() COMP 1027 Revision + Exam 63  Socket Programming (Windows) WSAStartup() socket() WSAStartup() bind() socket() listen() connect() accept() CLIENT SIDE send() recv() SERVER SIDE Waiting for Client’s requests recv() send() Listening to Specific Port close() close() WSACleanup() WSACleanup() COMP 1027 Revision + Exam 64 Lectures 10 ALU + Latches – ZOOM-IN  ALU controls [ALL] zx nx f no x x1 x2 x2&y2 0 AND16 x‘1 Out1 Out y Out1’ y1 16-bit x2+y2 y2 Full Adder y‘1 zy ny COMP 1027 Revision + Exam 66  ALU Controls Try the rest Hints: -A = A’ + 1 Also: A’ = -A – 1 S. Bagley, UNUK COMP 1027 Revision + Exam 67  Latch Vs Flip Flop Latch: - Level-triggered - Change anytime within e.g. Clock = high Flip-Flop: - Change only at the edge; Transition of Clock; Low → High Freeze after that - Edge Triggered (more precise) Will continue with Flip-Flops S. Bagley, UNUK COMP 1027 Revision + Exam 68 Exam  Assessment Strategy Combination of Coursework & Exam - Multiple assessed coursework, - TIMED, Exam condition, building on the weekly laboratory - End of Semester tasks Coursework Exam 75% 25% COMP 1027 Revision + Exam 70 Assessment Strategy School’s policy on the timed Exams: - TIMED, Exam condition, - Exact date & time: Exam Office will email you all (Exam TimeTable) Exam COMP 1027 Revision + Exam 71 Indicative Sections Binary/Boolean Arithmetic Numbering systems & converting between them - (binary, decimal, hex,…) - Negative numbers: 1’s, 2’s complements - Addition, subtractions,… Boolean Expressions COMP 1027 Revision + Exam 72 Indicative Sections Digital Logic Elementary, Combinatorial & Sequential Logic Including (only examples, not exhaustive. Any other can come) - What is it? What for?... - How to implement it? Work out the Boolean expression, from Truth Tables Simplify expressions Draw circuit diagram ….. COMP 1027 Revision + Exam 73 Indicative Sections Machine & Assembly Code What are they? Instructions and addressing How do they relate to the hardware (particularly CPU) COMP 1027 Revision + Exam 74 Indicative Sections Networking OSI model, layers (names, functions, protocols,…), pros/cons,…etc TCP/IP model, compared with OSI model Internet addressing, classes and class-less Network standards (representations,…etc.) Client-server & socket programming COMP 1027 Revision + Exam 75 Important Show ALL your working details when requested Final answer alone is NOT enough! Take the hints, from questions, and answer all what is required REMEMBER THIS! COMP 1027 Revision + Exam 76 All the BEST! COMP 1027 Revision + Exam 77 Summary 1 2 Everything we have EXAM Format LEARNED so far… COMP 1027 Revision + Exam 78 Questions  NEXT: Mock Exam