Interrupt Interface of 8086 and 8088 PDF

Interrupt Interface of 8086 and 8088 Behrooz Abdoli Electrical & Computer Engineering (ECE) Faculty Razi University B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Ins...

Interrupt Interface of 8086 and 8088 Behrooz Abdoli Electrical & Computer Engineering (ECE) Faculty Razi University B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Nonmaskable Interrupt ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor Interrupt Mechanism ❑ Transfer of program control is initiated by the occurrence of either an event internal to the microprocessor or an event in its external hardware. ❑ When an interrupt signal occurs, the MPU must suspend what it is doing in the main part of the program and pass control to a special routine that performs the function required by the device. ❑ The section of program to which control is passed is called the interrupt-service routine. B.Abdoli, Microprocessor Interrupt Mechanism B.Abdoli, Microprocessor Interrupt Mechanism ❑ Here we see that interrupt 32 occurs as instruction N of the program is being executed. ❑ When the MPU terminates execution of the main program in response to interrupt 32, it first saves information that identifies the instruction following the one where the interrupt occurred, instruction N + 1, and then picks up execution with the first instruction in the service routine. ❑ After this routine has run to completion, program control is returned to the point where the MPU originally left the main program, instruction N + 1, and then execution resumes. B.Abdoli, Microprocessor Interrupt Mechanism ❑ The 8088 and 8086 microcomputers are capable of implementing any combination of up to 256 interrupts. ❑ Interrupts are divided into five groups: external hardware interrupts, nonmaskable interrupt, software interrupts, internal interrupts, and reset. ❑The user defines the function of the external hardware, software, and nonmaskable interrupts. ▪ For instance, hardware interrupts are often assigned to devices such as the keyboard, printer, and timers. ❑On the other hand, the functions of the internal interrupts and reset are not user defined. They perform dedicated system functions. B.Abdoli, Microprocessor Interrupt Mechanism ❑ Hardware, software, and internal interrupts are serviced on a priority basis. Priority is achieved in two ways. ❑ First, the interrupt-processing sequence implemented in the 8088/8086 tests for the occurrence of the various groups based on the hierarchy. ❑ Second, each of the interrupts is given a different priority level by assigning it a type number. Type 0 identifies the highest priority interrupt, and type 255 identifies the lowest priority interrupt. B.Abdoli, Microprocessor Interrupt Mechanism ❑ A few of the type numbers are not available for use with software or hardware interrupts. This is because they are reserved for special interrupt functions of the 8088/8086, such as internal interrupts. ❑ For instance, within the internal interrupt group, the interrupt known as divide error is assigned to type number 0. Another internal interrupt, called overflow, is assigned the type number 4. ❑ The importance of priority lies in the fact that, if an interrupt-service routine has been initiated to perform a function assigned to a specific priority level, only devices with higher priority are allowed to interrupt the active service routine. B.Abdoli, Microprocessor Interrupt Mechanism ❑ A few of the type numbers are not available for use with software or hardware interrupts. This is because they are reserved for special interrupt functions of the 8088/8086, such as internal interrupts. ❑ For instance, within the internal interrupt group, the interrupt known as divide error is assigned to type number 0. Another internal interrupt, called overflow, is assigned the type number 4. ❑ The importance of priority lies in the fact that, if an interrupt-service routine has been initiated to perform a function assigned to a specific priority level, only devices with higher priority are allowed to interrupt the active service routine. B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor Interrupt Vector Table ❑ An address pointer table is used to link the interrupt type numbers to the locations of their service routines in the program-storage memory. ❑ Each of the 256 pointers requires two words (4 bytes) of memory and is always stored at an even-address boundary. The higher-addressed word of the two-word vector is called the base address. The lower addressed word of the vector is the offset Interrupt Vector Table ❑ Example: At what address are CS50 and IP50 stored in memory? ❑ Solution: Address = 4 * 50 = 200 Address = C816 Therefore, IP50 is stored at 000C816 and CS50 at 000CA16. B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor Interrupt Instruction B.Abdoli, Microprocessor Interrupt Instruction ❑ The trap flag (TF): If TF is set, the 8088 goes into the single-step mode of operation. When in the single-step mode, it executes an instruction and then jumps to a special service routine that may determine the effect of executing the instruction. This type of operation is very useful for debugging programs. ❑ The first two instructions, STI and CLI, permit manipulation of the interrupt flag through software. ▪ Execution of STI instruction enables the external interrupt request (INTR) input for operation—that is, it sets interrupt flag (IF). ▪ Execution of CLI disables the external interrupt input by resetting IF. B.Abdoli, Microprocessor Interrupt Instruction ❑ Executing the software-interrupt instruction INT n causes program control to be transferred to the subroutine pointed to by the vector for the number n specified in the instruction. ❑ For example, execution of the instruction INT 50 initiates execution of a subroutine whose starting point is identified by vector 50. ▪ First, the MPU saves the old flags on the stack, clears TF and IF, and saves the old program context, CS and IP, on the stack. ▪ Then it reads the values of IP50 and CS50 from addresses 000C816 and 000CA16, respectively, in memory, loads them into the IP and CS registers, calculates the physical address CS50:IP50, and starts to fetch instruction from this new location in program memory. B.Abdoli, Microprocessor Interrupt Instruction ❑ An interrupt-return (IRET) instruction must be included at the end of each interrupt service routine. It is required to pass control back to the point in the program where execution was terminated due to the occurrence of the interrupt. ❑ INTO is the interrupt-on-overflow instruction. This instruction must be included after arithmetic instructions that can result in an overflow condition, such as divide. ▪ It tests the overflow flag, and if the flag is found to be set, a type 4 internal interrupt is initiated. ▪ This condition causes program control to be passed to an overflow service routine located at the starting address identified by the vector IP4 at 0001016 and CS4 at 0001216. B.Abdoli, Microprocessor Interrupt Instruction ❑ The last two instructions associated with the interrupt interface are halt (HLT) and wait (WAIT). ❑ They produce similar responses by the 8088/8086 and permit the operation of the MPU to be synchronized to an event in external hardware. ❑ For instance, when HLT is executed, the MPU suspends operation and enters the idle state. It remains idle waiting for the occurrence of an external hardware interrupt or reset interrupt. ❑With the occurrence of either of these events, the MPU resumes execution with the corresponding service routine. B.Abdoli, Microprocessor Interrupt Instruction ❑ If the WAIT instruction is used instead of the HLT instruction, the MPU checks the logic level of the TEST input prior to going into the idle state. ❑Only if TEST is at logic 1 will the MPU go into the idle state. ❑While in the idle state, the MPU continues to check the logic level at TEST, looking for its transition to the 0 logic level. ❑As TEST switches to 0, execution resumes with the next sequential instruction in the program. B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor Enable/ Disable of Interrupts ❑ The ability to initiate an external hardware interrupt at the INTR input is enabled by setting IF or masked out by resetting it. ❑It affects only the external hardware-interrupt interface, not software interrupts, the nonmaskable interrupt, or internal interrupts. ❑Executing the STI instruction or the CLI instruction, respectively, does this through software. ❑ During the initiation sequence of a service routine for an external hardware interrupt, the MPU automatically clears IF. B.Abdoli, Microprocessor Enable/ Disable of Interrupts ❑ This masks out the occurrence of any additional external hardware interrupts. ❑In some applications, it may be necessary to permit other interrupts to interrupt the active service routine. ❑If this is the case, the interrupt flag bit can be set with an STI instruction in the service routine to reenable the INTR input. ❑Otherwise, the external hardware-interrupt interface is reenabled by the IRET instruction at the end of the service routine. B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ Let us now look at the signals of the external hardware interrupt interface of the 8088 and 8086 microcomputer systems. ❑We investigate two different mode interrupt interfaces: ▪ Minimum-Mode Interrupt Interface ▪ Maximum-Mode Interrupt Interface B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ Minimum-Mode Interrupt Interface: ❑ Here we see that it includes the multiplexed address/data bus and dedicated interrupt signal lines INTR and INTA. ❑ We also see that external circuitry is required to interface the interrupt inputs, INT32 through INT255, to the 8088’s interrupt interface. B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ This interface circuitry must identify which of the pending active interrupts has the highest priority and then pass its type number to the microprocessor. ❑ The input at the INTR line signals the 8088 that an external device is requesting service. The 8088 samples this input during the last clock period of each instruction execution cycle. ❑ Its active 1 level must be maintained until tested by the 8088. ❑Moreover, the logic 1 at INTR must be removed before the service routine runs to completion; otherwise, the same interrupt may get acknowledged a second time. B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ When an interrupt request has been recognized by the 8088, it signals this fact to external circuitry. It does this with pulses to logic 0 at its INTA output. ❑ Actually, there are two pulses produced at INTA during the interrupt acknowledge bus cycle: ▪ The first pulse signals external circuitry that the interrupt request has been acknowledged. ▪ The second pulse tells the external circuitry to put the type number on the data bus. B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ Note that the lower eight lines of the address/data bus, AD0 through AD7, are also part of the interrupt interface. ▪ During the second cycle in the interrupt acknowledge bus cycle, external circuitry must put an 8-bit type number on bus lines AD0 through AD7. ❑ The 8088 reads this number off the bus to identify which external device is requesting service. ❑It uses the type number to generate the address of the interrupt’s vector in the pointer table and to read the new values of CS and IP into the corresponding internal registers. B.Abdoli, Microprocessor  External Hardware Interrupts signals ❑ Maximum-Mode Interrupt Interface: B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ In the maximum mode system, the 8288 bus controller produces the INTA and ALE signals. ❑ Whenever the 8088 outputs an interrupt-acknowledge bus status code, the 8288 generates pulses at its INTA output to signal external circuitry. B.Abdoli, Microprocessor External Hardware Interrupts signals ❑ A second change is that the 8088 provides a new signal for the interrupt interface. This output, labeled LOCK , is called the bus priority lock signal. ❑LOCK is applied as an input to a bus arbiter. In response to this signal, the arbitration logic ensures that no other device can take over control of the system bus until the interrupt-acknowledge bus cycle is complete. ❑ the only difference between 8086 circuit and that of the 8088 microcomputer is that the complete 16-bit data bus is used to transfer data between the MPU and interrupt interface circuits. B.Abdoli, Microprocessor Topics A ❑Interrupt Mechanism, Types, and Priority ❑Interrupt Vector Table ❑Interrupt Instructions ❑Enabling/Disabling of Interrupts ❑External Hardware-Interrupt Interface Signals ❑External Hardware-Interrupt Sequence B.Abdoli, Microprocessor External Hardware Interrupts ❑ The interrupt sequence begins when an external device requests service by activating one of the interrupt inputs, INT32 through INT255, of the 8088’s external interrupt interface circuit. ❑ The external interface circuitry evaluates the priority of this input. If there is no other interrupt already in progress or if this interrupt is of higher priority than the one presently active, the external circuitry issues a request for service to the MPU. ❑ If INT50 is the only active interrupt request input, the external circuitry switches INTR to logic 1. This tells the 8088 that an interrupt is pending for service. To ensure that it is recognized, the external circuitry must maintain INTR active until an interrupt- acknowledge pulse is issued by the 8088. B.Abdoli, Microprocessor External Hardware Interrupts ❑ Note that it tests first for the occurrence of an internal interrupt, then the occurrence of the nonmaskable interrupt, and finally checks the logic level of INTR to determine if an external hardware interrupt has occurred. ❑ If INTR is logic 1, a request for service is recognized. if IF is at logic 1, external hardware interrupts are enabled and the service routine is initiated. B.Abdoli, Microprocessor External Hardware Interrupts B.Abdoli, Microprocessor External Hardware Interrupts ❑ Let us assume that IF is set to permit interrupts to occur when INTR is tested as 1. ❑ During T1 of the first bus cycle, we see that a pulse is output on ALE along with putting the address/data bus in the high-Z state. ❑During periods T2 and T3, INTA is switched to logic 0. This signals external circuitry that the request for service is granted. ❑In response to this pulse, the logic 1 at INTR can be removed. B.Abdoli, Microprocessor External Hardware Interrupts ❑ During the second interrupt-acknowledge bus cycle, a similar signal sequence occurs. However, this interrupt-acknowledge pulse tells the external circuitry to put the type number of the active interrupt on the data bus. ❑ External circuitry gates one of the interrupt codes 32 through 255, onto data bus lines AD0 through AD7. ❑ More detail in chapter 11- section 6 B.Abdoli, Microprocessor External Hardware Interrupts ❑ Example: The circuit is used to count interrupt requests. The interrupting device interrupts the microprocessor each time the interrupt-request input signal transitions from 0 to 1. The corresponding interrupt type number generated by the 74LS244 is 60H. B.Abdoli, Microprocessor External Hardware Interrupts ❑ A- Describe the operation of the hardware for an active request at the interrupt-request input. ❑ B- What is the value of the type number sent to the microprocessor? ❑ C- Assume that the original values in the segment registers are (CS) = (DS) = 1000H and (SS) = 4000H; the main program is located at offsets of 200H from the beginning of the original code segment; the count is held at an offset of 100H from the beginning of the current data segment; the interrupt-service routine starts at offset 1000H from the beginning of another code segment that begins at address 2000H:0000H; and the stack starts at an offset of 500H from the beginning of the current stack segment. Make a map showing the organization of the memory address space. ❑ D- Write the main program and the service routine for the circuit so that the positive transitions at INTR are counted as a decimal number. B.Abdoli, Microprocessor External Hardware Interrupts ❑ Solution: ❑ A- Analysis of the circuit shows that a positive transition at the CLK input of the flip- flop (interrupt request) makes the Q output of the flip-flop logic 1 and presents a positive level signal at the INTR input of the 8088. When the 8088 recognizes this as an interrupt request, it responds by generating the ?signal. The logic 0 output on this line clears the flip-flop and enables the 74LS244 buffer to present the type number to the 8088. This number is read off the data bus by the 8088 and is used to initiate the interrupt-service routine. ❑ B- From the inputs and outputs of the 74LS244, we see that the type number is AD7... AD1AD0 = 60H B.Abdoli, Microprocessor External Hardware Interrupts ❑C- B.Abdoli, Microprocessor External Hardware Interrupts ❑C- Here we see that the type 60H vector is located in the interrupt vector table at address 60H*4 = 180H. Note that the byte-wide memory location used for Count is at address 1000H:0100H. This part of the memory address space is identified as the program data area in the memory map. The main part of the program, entered after reset, starts at address 2000H:1000H. On the other hand, the service routine is located at address 2000H:1000H in a separate code segment. For this reason, the vector held at 180H of the interrupt-vector table is (CS) = 2000H and (IP) = 1000H. Finally, the stack begins at 4000H:0000H with the current top of the stack located at 4000H:0500H. B.Abdoli, Microprocessor External Hardware Interrupts ❑ D- The flowcharts show how the main program and interrupt-service routines are to function. ❑ The corresponding software is given in the next page. B.Abdoli, Microprocessor External Hardware Interrupts B.Abdoli, Microprocessor Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Nonmaskable Interrupt ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor 82C59A Programmable Interrupt Controller ❑ The 82C59A is a peripheral IC that is designed to simplify the implementation of the interrupt interface in the 8088- and 8086-based microcomputer systems. ❑ This interface consists of eight data bus lines, D0 through D7, and control signals read (RD ), write (WR ), and chip select (CS ). ❑Control input CS must be at logic 0 to enable the host processor interface, WR and RD signal the 82C59A whether data are to be written into or read from its internal registers. ❑ A0 input involved in the selection of the internal register that is accessed during read and write operations. B.Abdoli, Microprocessor 82C59A Programmable Interrupt Controller B.Abdoli, Microprocessor Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Nonmaskable Interrupt ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Interrupt Interface Circuit Using 82C59A ❑ Next figure includes an interrupt interface circuit for a minimum-mode microcomputer system that is made with the 82C59A. B.Abdoli, Microprocessor B.Abdoli, Microprocessor Interrupt Interface Circuit Using 82C59A ❑ Next figure includes an interrupt interface circuit for a maximum-mode microcomputer system that is made with the 82C59A. B.Abdoli, Microprocessor Interrupt Interface Circuit Using 82C59A ❑ Example: Analyze the circuit below and write an appropriate main program and a service routine that counts as a decimal number the positive edges of the clock signal applied to the IR0 input of the 82C59A. B.Abdoli, Microprocessor Interrupt Interface Circuit Using 82C59A ❑ Solution: The microprocessor addresses to which the 82C59A in the circuit shown responds depend on how the CS signal for the 82C59A is generated as well as the logic level of address bit A1, connected to input A0. Note that the A0 address line of the microprocessor is not used in the circuit and therefore it is a don’t-care bit. Thus, if A0 is taken as 0, the 82C59A responds to A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0 = 11111111000000002 for A1 = 0, and = 11111111000000102 for A1 = 1, B.Abdoli, Microprocessor Interrupt Interface Circuit Using 82C59A ❑ Let assume that use interrupt type 72 to service an interrupt. ❑ In the interrupt-vector table we need to set up the type 72 vector. The type 72 vector is located at 4 × 72 = 288 = 120H. ❑ At address 120H we need to place the offset of the service routine and at address 122H the code segment value of the service routine. Interrupt Interface Circuit Using 82C59A ❑ In the data area we need a location to keep a decimal count of the edges of the input clock. ❑ Let us assume that it is location 01000H. ❑ The stack segment starts at 0FF00H and ends at 0FFFFH. ❑ The start address of the main program is denoted as START, and that of the service routine is denoted as SRV72. Interrupt Interface Circuit Using 82C59A ❑ First we establish various segments for data and stack. ;MAIN PROGRAM CLI ; disabled interrupts START: MOV AX, 0 ;Extra segment at 00000H MOV ES, AX MOV AX, 1000H ;Data segment at 01000H MOV DS, AX MOV AX, 0FF00H ;Stack segment at 0FF00H MOV SS, AX MOV SP, 100H ;Top of stack at 10000H Interrupt Interface Circuit Using 82C59A ❑ Next we can set up the IP and CS for the type 72 vector in the interrupt vector table. MOV AX, OFFSET SRV72 ;Get offset for the service routine MOV [ES:120H], AX ;Set up the IP MOV AX, SEG SRV72 ;Get code segment for the service routine MOV [ES:122H], AX ;Set up the CS ❑ For simplicity let us use the following instruction to wait for the interrupt: HERE: JMP HERE ;Wait for an interrupt Interrupt Interface Circuit Using 82C59A ❑ The operations interrupt-service routine can be implemented using the following instructions: SRV72: PUSH AX ;Save register to be used MOV AL, [COUNT] ;Get the count INC AL ;Increment the count DAA ;Decimal adjust the count MOV [COUNT], AL ;Save the new count POP AX ;Restore the register IRET ;Return from interrupt Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Nonmaskable Interrupt ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Software Interrupts ❑ The INT n instruction is used to initiate a software interrupt. ❑ The software interrupt service routine vectors are also located in the memory locations in the vector table. ❑ The mechanism by which a software interrupt is initiated is similar to that described for the external hardware interrupts. ❑ However, no external interrupt-acknowledge bus cycles are initiated. Instead, control is passed to the start of the service routine immediately upon completion of execution of the interrupt instruction. B.Abdoli, Microprocessor Software Interrupts ❑ Software interrupts are of higher priority than the external interrupts and are not masked out by IF. ❑ The software interrupts are actually vectored subroutine calls. A common use of these software routines is as emulation routines for more complex functions. ❑ For instance, INT 50 could define a floating-point addition instruction and INT 51 a floating-point subtraction instruction. ❑ Other examples of their use are for supervisor calls from an operating system and for testing external hardware interrupt service routines. B.Abdoli, Microprocessor Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Non-maskable Interrupts ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Non-maskable Interrupts ❑ The non-maskable interrupt (NMI) is another interrupt that is initiated from external hardware. However, it differs from the other external hardware interrupts in several ways. ▪ First, as its name implies, it cannot be masked out with the interrupt flag. ▪ Second, requests for service by this interrupt are signaled to the 8088 or 8086 microprocessor by applying logic 1 at the NMI input, not the INTR input. ▪ Third, the NMI input is positive edge-triggered. B.Abdoli, Microprocessor Non-maskable Interrupts ❑ If the contents of the NMI latch are sampled as being active for two consecutive clock cycles, it is recognized and at completion of the current instruction the non-maskable interrupt sequence is initiated. ❑ Just as with the other interrupts we have studied, initiation of NMI causes the current flags, current CS, and current IP to be pushed onto the stack. ❑ Moreover, the interrupt-enable flag is cleared to disable all external hardware interrupts. ❑ Next the MPU fetches the words of the NMI vector from memory and loads them into IP and CS. B.Abdoli, Microprocessor Non-maskable Interrupts ❑ It automatically vectors from the type 2 vector location in the pointer table. This vector is stored in memory at word addresses 0008H and 000AH. ❑ Typically, the NMI is assigned to hardware events that must be responded to immediately. ❑Two examples are the detection of a power failure and detection of a memory-read error. Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Non-maskable Interrupts ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Reset ❑ The RESET input of the 8088 and 8086 microprocessors provides a hardware means for initializing the microcomputer. ❑ This is typically done at power-up to provide an orderly startup of the system. ❑ However, some systems, such as a personal computer, also allow for a warm start—that is, a software-initiated reset. B.Abdoli, Microprocessor Reset ❑ The 8284 contains circuitry that makes it easy to implement the hardware reset function. This circuit is used to detect an active reset input and synchronize the application and removal of the RESET signal with the clock. ❑ Note that the RES input (pin 11) of the clock generator is attached to an RC circuit. The signal at RES is applied to the input of an internal Schmitt trigger circuit. ❑If the voltage across the capacitor is below the 1-logic-level threshold of the Schmitt trigger, the RESET output (pin 10) stays at logic 1. This output is supplied to the RESET input at pin 21 of the 8088. B.Abdoli, Microprocessor Reset ❑ At the RESET input of the 8088, this signal is synchronized to the 0-to-1 edge of CLK to create an internal reset signal. ❑ RESET must be held at logic 1 for a minimum of four clock cycles; otherwise, it will not be recognized. B.Abdoli, Microprocessor Reset ❑ When RESET is recognized as active, the 8088 terminates operation, puts its buses in the high-Z state, and switches the control signals to their inactive states. ഥ , DT/R ❑ signal lines SSO, IO/M ഥ , DEN, 𝑊R, RD, and INTA are first forced to logic 1 for one clock interval and then are put in the high-Z state synchronously with the positive edge of the next clock pulse. ❑ The 8088 remains in this state until the RESET input is returned to logic 0. B.Abdoli, Microprocessor Reset ❑ When the MPU recognizes the return to logic 0 at the RESET input, it initiates its internal initialization routine. ❑At completion of initialization, the flags are all cleared, the instruction pointer is set to 0000H, the CS register is set to FFFFH, the DS, SS, and ES registers are set to 0000H, and the instruction queue is emptied. ❑ Since the flags were all cleared as part of initialization, external hardware interrupts are disabled. B.Abdoli, Microprocessor Reset ❑ The code segment register contains FFFFH and the instruction pointer contains 0000H. ❑Therefore, program execution begins at address FFFF0H after reset. ❑This storage location can contain an instruction that will cause a jump to the startup program that is used to initialize the rest of the microcomputer system’s resources, such as I/O ports, the interrupt flag, and data memory. B.Abdoli, Microprocessor Topics B ❑82C59A Programmable Interrupt Controller ❑Interrupt Interface Circuits Using the 82C59A ❑Software Interrupts ❑Non-maskable Interrupts ❑Reset ❑Internal Interrupt Functions B.Abdoli, Microprocessor Internal Interrupts ❑ Internal interrupts differ from external hardware interrupts in that they occur due to the result of executing an instruction, not an event that takes place in external hardware. ❑ That is, an internal interrupt is initiated because of a condition detected before, during, or after execution of an instruction. ❑ In this case, a routine must be initiated to service the internal condition before resuming execution of the same or next instruction of the program. ❑ Internal interrupts are not masked out with the interrupt enable flag. B.Abdoli, Microprocessor Internal Interrupts ❑ Here we find divide error, overflow error, single step, and breakpoint. ❑ Each of these functions is assigned a unique type number. ❑ Notice that they are the highest- priority type numbers. ❑ Let us now look at each of these internal functions in more detail. B.Abdoli, Microprocessor Internal Interrupts: Divide Error ❑ The divide error function represents an error condition that can occur in the execution of the division instructions. ❑ If the quotient that results from a DIV (divide) instruction or an IDIV (integer divide) instruction is larger than the specified destination, a divide error has occurred. ❑ This condition causes automatic initiation of a type 0 interrupt and passes control to a service routine whose starting point is defined by the values of IP0 and CS0 at addresses 00000H and 00002H, respectively, in the pointer table. B.Abdoli, Microprocessor Internal Interrupts: Overflow Error ❑ It can result from the execution of any arithmetic instruction. Whenever an overflow occurs, the overflow flag gets set. ❑Unlike divide error, the transfer of program control to a service routine is not automatic at occurrence of the overflow condition. Instead, the INTO (interrupt on overflow) instruction must be executed to test the overflow flag (OF) and determine if the overflow service routine should be initiated. ❑ If the overflow flag is tested and found to be set, a type 4 interrupt service routine is initiated. ❑ For instance, it could cause a message to be displayed to specify that an overflow has occurred. B.Abdoli, Microprocessor Internal Interrupts: Single Step ❑ If the trap flag (TF) bit in the flags register is set, the single-step mode of operation is enabled. This flag bit can be set or reset under software control. ❑ When TF is set, the MPU initiates a type 1 interrupt to the service routine. ❑ The service routine could include a WAIT instruction. In this way, a transition to logic 0 at the TEST input of the 8088 or 8086 could be used as the mechanism for stepping through a program one instruction at a time. ❑This single-step operation can be used as a valuable software debugging tool. B.Abdoli, Microprocessor Internal Interrupts: Breakpoint Interrupt ❑ The breakpoint function can also be used to implement a software diagnostic tool. A breakpoint interrupt is initiated by execution of the breakpoint instruction. ❑ This instruction can be inserted at strategic points in a program that is being debugged to cause execution to be stopped automatically. ❑Breakpoint interrupt can be used in a way similar to that of the single-step option. ❑ The breakpoint service routine can stop execution of the main program, permit the programmer to examine the contents of registers and memory, and allow for the resumption of execution of the program down to the next breakpoint. B.Abdoli, Microprocessor