FPGA Design & Implementation (PDF)

FPGA  FPGA Overview Main Verilog Outlines Vivado Xilinx Tool Artix-7 FPGA Basys 3 Board Slight Overview FPGA Field-Programmable Gate Array (FPGA) is a type of sequential programmable logic devices that include both gates Combinationa...

FPGA  FPGA Overview Main Verilog Outlines Vivado Xilinx Tool Artix-7 FPGA Basys 3 Board Slight Overview FPGA Field-Programmable Gate Array (FPGA) is a type of sequential programmable logic devices that include both gates Combinational and flip‐flops. PLD It is a VLSI circuit that can be programmed at the user’s location. A typical FPGA consists of an array of millions of logic blocks, surrounded by programmable I/O blocks and connected via programmable interconnections. Logic block consists of lookup tables: contains implementation (or truth table) of logic gates multiplexers, and Sequential PLD  Consider LUT as ROM that can be used to implement combinational logic circuits Slice is 4 logic cells Configurable logic block is 2 slices  Rapid Prototyping: Quickly develop and iterate on custom chip designs at lower costs Why Parallel Processing: Ideal for high-speed tasks like DSP and FPGA image processing Performance Optimization: Tailored designs achieve better performance than general- purpose processors  FPGA Vs Microcontrolle r FPGA is a highly configurable digital IC allowing the user to create custom digital circuits (that is, it is reprogrammable on the hardware level) Microcontroller is considered as a general-purpose application specific IC (ASIC) device that is primarily software configurable. Microcontrollers cost less and are easier to use FPGA typically consumes more power than microcontrollers. Microcontroller is optimized for low power consumption, suitable for battery- powered applications. FPGA design can also handle parallel inputs simultaneously, whereas microcontrollers can only read one line of code at a time To Whom Engineers who design and implement digital circuits and systems using FPGAs Who work with hardware description languages (HDLs) such as SystemVerilog, Verilog, and VHDL to create and test FPGA designs Who have a strong interest in digital design and want to learn about FPGA development Digital Design Flow Classica l Digital Design Flow FPGA Design An FPGA workflow is similar to a Flow semiconductor design flow FPGA Design cycle ASIC Design Development Flow of FPGA-based System In programming process, a system is transformed from an abstract textual HDL description to a device cell- level configuration then downloaded to FPGA In validation process, checks whether the system meets the functional specification and performance goals Programming Validati process process FPGA development workflow Involves the following steps: 1.Requirements analysis and system architecture design 2.RTL design or high-level synthesis 3.Behavioral simulation 4.Logic synthesis 5.Implementation (placement and routing) 6.Timing and power analysis 7.Bitstream generation 8.Hardware configuration and testing  HDL High-level of designing digital systems Introduction A hardware description HDLs enable the description of languages (HDLs) is way to large digital systems without describe digital circuitry using schematics, which become using a text-based language impractical for complex designs Designers can focus on Modern HDLs support automated functionality at a high level, synthesis, where CAD tools delaying circuit implementation convert functional descriptions details until later in the (e.g., truth tables) into gate- design cycle level circuitry for real Supports scalable designs hardware across different logic families using a top-down approach The most common types are Verilog and VHDL HDL Abstraction HDLs were originally defined to be able to model behavior at multiple levels of abstraction The highest level of abstraction is the system level HDLs are designed to model behavior at all of these levels with the exception of the material level Verilog Constructs Verilog is case sensitive Each Verilog assignment, definition or declaration is terminated with a semicolon (;). Comments in Verilog are supported in two ways. The first way is called a line comment and is preceded with two slashes (i.e., //). Second is the block comment and begins with. All user-defined names in Verilog must start with an alphabetic letter, not a number. User-defined names are not allowed to be the same as any Verilog keyword Verilog is a weakly typed (or loosely typed) language, meaning that it permits assignments between different data types. Verilog Value Set and Data Types Verilog supports four basic values that a signal can take on: 0, 1, X, and Z In Verilog, every signal, constant, variable, and function must be assigned a data type. Some data types are synthesizable, while others are only for modeling abstract behavior. Two general data types: Net and Variable Net Data Type Models an interconnection (aka., a net) between components. A signal with a net data type must be driven at all times and updates its value when the driver value changes The types that fall into this category: Variabl e Data Type Models logic storage. Hold the value assigned to them until their next assignment If its value is X, thus its state is not known Verilog Constructs - Vectors Verilog Constructs – Arrays Verilog Constructs – Numbers Representations If a number is simply entered into Verilog, it is treated as an integer Verilog also supports an optional bit size and sign of a number. Syntax for specifying the base of a number: Note that specifying the size is optional. If it is omitted, the number will default to a 32- bit vector with leading zeros added, as necessary. Verilog Constructs – Module A Verilog design describes a single system in a single file. The file has the suffix *.v. Within the file, the system description is contained within a module. The module includes the interface to the system (i.e., the inputs and outputs) and the description of the behavior Modules can include instantiations of lower- level modules to support Verilog Constructs – Module The user-defined port names are case sensitive The port directions are declared to be one of the three types: input, output, and inout. A signal that is used for internal connections within a system is declared within the module before its first use Verilog Constructs – Parameters A parameter, or constant, is useful for representing a quantity that will be used multiple times in the architecture. The syntax for declaring a parameter Constructs – Compiler Directives Provide additional information to the simulation tool on how to interpret the Verilog model Placed before the module definition and is preceded with a backtick (i.e., `) Modelling Concurrent Functionality and Structural Design in Verilog Verilog Constructs - Operators Verilog uses the keyword assign to denote a continuous signal assignment. It models combinational logic There are arithmetic, shift, bitwise, and relational operators. The + and - operators can also be used as unary operators, as in -a. During synthesis, the + and - operators infer the adder and subtractor Synthesis of the multiplication operator * depends on synthesis software and target device technology. Commonly, FPGAs contain prefabricated combinational multiplier blocks. The /, %, and ** operators usually cannot be Verilog Operators - Shift 0's are shifted in for a logical shift operation (i.e., >> and ) The sign bits (i.e., the MSB) are shifted in for the >>> operation and the 0's are shifted in for the