GIU_2503_64_19546_2024-09-24T15_37_28 (1).pdf

Micro-Controllers Dr. Moheb Mekhaiel Lecture 2 24. September 2024 1 Slide credits Slide credits Presentation slides based on work by Prof. Ansgar Meroth Founding Dean GIU...

Micro-Controllers Dr. Moheb Mekhaiel Lecture 2 24. September 2024 1 Slide credits Slide credits Presentation slides based on work by Prof. Ansgar Meroth Founding Dean GIU Faculty of Engineering 2 2  Outline today The instruction cycle / Instruction Set Comparing CISC and RISC Key properties of Microcontrollers Review of digital logic and Boolean operations Signed-Complement System, Hexadecimal K-maps Sequential Logic (intro) Dr. Moheb Mekhaiel 3  The instruction cycle 1. Fetch the instruction Example: Can ADD R16, R17 ; Add value in R16 to value in R17 DEC R17 ; Minus 1 from the value contained in R17 2. Decode the instruction MOV R18, R16 ; Copy the value in R16 to R18 JMP END ; Jump to the label END 3. Fetch operand(s) Arithmetic/logic instructions 4. Execute Transfer instructions Jump instructions 5. Store results I/O instructions b += a; In C-Language it is easier: b--; 6. Increment Prog Cnt c=a; 4  The µC and its memories (ex. ATMega32) 0x0000 0x000 Can 32 registers 0x0000 - 0x001F Application 64 I/O registers 0x0020 - 0x005F flash 2x512 section 0x0060 – 0x085F bytes Internal SRAM (2x1024 bytes) 0x2FF 0x085F Boot flash 0x0FFF section 0x3FFF Program memory (Flash) Data memory EEPROM memory ATMega32: 32kB ATMega32: 2kB ATMega32: 1024 bytes 5  Instruction Set Architecture The ISA (Instruction Set Architecture) defines: Operations that the processor can execute The mechanism of Data Transfer and how to access data Control Mechanisms (branch, jump, etc.) interrupt and exception handling external I/O handling The main ISAs are CISC and RISC: CISC stands for Complex Instruction Set Computer RISC stands for Reduced Instruction Set Computer 6  Types of microcontrollers based on instruction set CISC (Complex Instruction Set Computer): the CPU is designed to execute one or single complex command. It can execute multiple instructions by using a single instruction. It has a small-sized program and that is its advantage. But because of the large size of its instruction set with many addressing modes, it takes a multiple machine cycle to execute RISC (Reduced Instruction Set Computers): In this kind of microcontroller, the CPU is designed to execute small and simple commands. It takes only one machine cycle to execute a single instruction. 7 Comparing CISC and RISC CISC RISC MULT 2:3, 5:2 LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A One Complex instruction. Several simple instructions each with one clock cycle complex instruction, Reduced number of complex hardware, instruction, smaller HW, smaller memory larger memory 8  The CISC Approach The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction-set Includes multi-clock Instructions Has a large amount of different (in length) and complex instructions Direct Memory-to-memory instructions Small code sizes (use less number of instructions) Requires more transistors 9  The RISC Approach RISC use simple instructions executed in one clock cycle. Because there are more lines of code, more program memory is needed to store the assembly level instructions. Have to get memory data to register through "LOAD" and "STORE“ Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. 10  RISC versus CISC RISC CISC RISC is a reduced instruction set. CISC is a complex instruction set. It optimizes the performance by It optimizes the performance by focusing on software. focusing on hardware. The number of instructions is less The number of instructions is as compared to CISC. more as compared to RISC. The addressing modes are less. The addressing modes are more. fixed instruction format. variable instruction format. The RISC consumes low power. The CISC consumes higher power. Requires more RAM. Requires less RAM. 11  Key properties of Microcontrollers clock / operating frequency Notice: one instruction can require several cycles Can MIPS Million Instruction per Second Data width 8-bit, 16-bit, 32-bit Semiconductor process The minimum size and spacing on chip affects consumption Size of memory Typically Flash less than 1 Mbyte program and 256 Byte EEPROM Quality of ADC Bits per sample / sampling rate / number of channels I/O Number, availability of interfaces like UART, CAN, LIN, I2C, SP Timers Number, frequency, Bit width Instruction set RISC has smaller instruction set Choose the most cost effective / simple controller that can realize your application! 12  Binary / Hexadecimal Decimal Binary Hexadecimal 0 0000 0 Consider 1 hexadecimal digit as 4 binary bits: 1 0001 1 2 0010 2 3 0011 3 1001 1111 0101 4 0100 4 5 0101 5 9 F 5 6 0110 6 7 0111 7 0010 1001 1011 8 1000 8 9 1001 9 10 1010 A 29B in binary? 11 1011 B 12 1100 C 13 1101 D 14 1110 E 15 1111 F 13  2’s complement If you are presenting numbers by only one byte and would like to preset +ve and –ve integers as well we use the rule of 2’s complement to present negative numbers Rule: Complement each bit including the left-most sign bit (resulting in the 1’s complement) Add 1 to the result Example: 13 is represented in binary as 01101 After complementing: 10010 After adding 1: 10011 what is the largest positive number that can be presented with 8-bits? 14  AND: Conjunction Function table Electrical realisation Timing Diagram 2 series switches Both on → lamp on © Prof. Ansgar Meroth 15  OR: Disjunction Function table Electrical realisation Timing Diagram 2 parallel switches, at least one on → lamp on © Prof. Ansgar Meroth 16  NOT: Negation Function table Electrical realisation Timing Diagram Switch on → lamp off and vice versa © Prof. Ansgar Meroth 17  NAND: (NOT AND) Function table Electrical realisation Timing Diagram Both switches pressed (openers) & lamp off © Prof. Ansgar Meroth 18  NOR: (NOT OR) Function table Electrical realisation Timing Diagram One Switch on (Opener) → lamp off © Prof. Ansgar Meroth 19  XOR: Exclusive-OR, Antivalence Function table Electrical realisation Timing Diagram If one switch is on, the other has to be off to turn on the lamp © Prof. Ansgar Meroth 20  XNOR: Exclusive-NOR, Equivalence Function table Electrical realisation Timing Diagram Lamp is on when both switches have same state © Prof. Ansgar Meroth 21  Example A machine is operating when: The Safety circuit is closed AND The cabinet is closed AND [ The ON-Button is pressed manually OR The machine gets a start PLC signal ] © Prof. Ansgar Meroth 22  Example A machine is operating when: The Safety circuit is closed AND The cabinet is closed AND [ The ON-Button is pressed manually OR The machine gets a start PLC signal ] © Prof. Ansgar Meroth 23  Simplifying Truth Tables Methods to simplify Truth Tables By using Laws of Boolean By using Karnaugh Maps Algebra (also called K-maps) 24 Summary of Boolean Rules A.0=0 A+0=A A.1=A A+1=1 A.A=A A+A=A 𝐴 𝐴ҧ = 0 𝐴 + 𝐴ҧ = 1 𝐴 =𝐴 𝐴 + 𝐴𝐵 = 𝐴 (𝐴 + 𝐵)(𝐴 + 𝐶) = 𝐴 + 𝐵𝐶 ҧ =𝐴+𝐵 𝐴 + 𝐴𝐵 𝐴 𝐵 + 𝐶 = 𝐴𝐵 + 𝐴𝐶 𝐴 + 𝐵𝐶 = (𝐴 + 𝐵)(𝐴 + 𝐶) 𝐴𝐵 = 𝐴ҧ + 𝐵ത 𝐴 + 𝐵 = 𝐴ҧ𝐵ത 25  K-maps Procedure: Extract the simplest expression Fill the map with 1s in the corresponding cells according to the truth table Group adjacent cells containing 1s. Groups should be powers of 2 (1 cell, 2 cells, 4 cells, 8 cells,...) A cell could be part of multiple groups Expression is extracted by finding the commons Difference between any two adjacent cells is always one term only, which appears complemented in one cell and un-complemented in the other Dr. Jasmine Zaghloul 26  K-maps The number of adjacent cells that may be combined must always represent a number that is a power of two, such as 1, 2, 4 and 8 As more adjacent cells are combined, we obtain a product term with fewer literals One cell represents one minterm, giving a term with 3 literals Two adjacent cell represent a term with 2 literals Four adjacent cells represent a term with 1 literal Eight adjacent cells encompass the entire map and produce a function that is always equal to logic 1 Dr. Jasmine Zaghloul 27  2 Variable K-maps B A Dr. Jasmine Zaghloul 28  3 Variable K-maps B A C Dr. Jasmine Zaghloul 29  K-maps: 3 variable A B C F 𝐵 0 0 0 0 0 1 0 0 1 0 BC 00 01 11 10 2 0 1 0 1 A 0 1 3 2 1 1 3 0 1 1 1 0 4 5 7 6 4 1 0 0 0 𝐴 1 5 1 0 1 0 6 1 1 0 0 𝐶 7 1 1 1 0 Dr. Jasmine Zaghloul 30 4 Variable K-maps C B A D 31  K-maps: 4 variable A B C D F 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 1 𝑪 3 0 0 1 1 1 4 0 1 0 0 0 CD 00 01 11 10 5 0 1 0 1 0 AB 0 1 3 2 1 0 1 1 6 0 1 1 0 0 00 4 5 7 6 7 0 1 1 1 0 01 8 1 0 0 0 0 𝑩 12 13 15 14 9 1 0 0 1 0 11 10 1 0 1 0 0 𝑨 8 9 11 10 11 1 0 1 1 0 10 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 𝑫 15 1 1 1 1 0 Dr. Jasmine Zaghloul 32  Explaining the Rules 33 https://www.gatevidyalay.com/k-maps-karnaugh-maps-solved-examples/  Explaining the Rules 34 https://www.gatevidyalay.com/k-maps-karnaugh-maps-solved-examples/  Some Basic Cases C C C CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 0 0 0 0 00 1 1 0 0 00 0 0 0 0 01 1 1 1 1 B 01 1 1 0 0 B 01 0 0 0 0 B A 11 1 1 1 1 A 11 1 1 0 0 A 11 1 1 0 0 10 0 0 0 0 10 1 1 0 0 10 1 1 0 0 D D D 𝐹=𝐵 𝐹 = 𝐶ҧ 𝐹 = 𝐶ҧ ∙ 𝐴 35  Some Basic Cases C C C CD CD CD AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 00 1 0 0 1 00 0 0 0 0 00 0 0 0 0 01 1 0 0 1 01 0 0 0 0 01 0 0 0 0 B B B A 11 1 0 0 1 A 11 0 1 1 0 A 11 0 1 0 0 10 1 0 0 1 10 0 0 0 0 10 0 0 0 0 D D D ഥ 𝐹=𝐷 𝐹 =𝐴∙𝐵∙𝐷 𝐹 = 𝐴 ∙ 𝐵 ∙ 𝐷 ∙ 𝐶ҧ 36  Some Basic Cases C C CD CD AB 00 01 11 10 AB 00 01 11 10 00 0 0 1 0 00 1 0 0 1 01 0 0 0 0 01 0 0 0 0 B B A 11 0 1 0 0 0 0 0 0 A 11 10 0 0 0 0 10 1 0 0 1 D D 𝐹 = 𝐴 ∙ 𝐵 ∙ 𝐷 ∙ 𝐶ҧ + 𝐴ҧ ∙ 𝐵ത ∙ 𝐶 ∙ 𝐷 𝐹 = 𝐵ത ∙ 𝐷 ഥ 37  A B C F Example 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 3 0 1 1 1 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 SUM of Products Products of Sums 𝐵 𝐵’ BC BC 00 01 11 10 00 01 11 10 A A 0 1 3 2 0 1 1 3 1 2 0 0 0 0 4 5 7 6 4 5 7 6 1 𝐴′ 1 0 0 0 𝐴 1 𝐶 𝐶′  Example 𝐵 𝐵’ BC BC 00 01 11 10 00 01 11 10 A A 0 1 3 2 0 1 1 3 1 2 0 0 0 0 4 5 7 6 4 5 7 6 1 𝐴′ 1 0 0 0 𝐴 1 𝐶 𝐶’ 𝑭 = 𝑩𝑪 + 𝐴′ 𝐵 𝑭 = 𝑩. (𝐴′ +𝐶) = 𝑨′ 𝑩 + 𝑩𝑪 B C F A’ B Dr. Jasmine Zaghloul  Sequential Logic In combinational logic (digital gates), the output is always the same for the same inputs A sequential circuit has a memory, i.e. its state is derived from its history Ynew = f (X, Yold) So, how can we keep the old state? It is done by feedback 40  Latches and Flip Flops A Latch is an electronic circuit with two stable states. It is used as data storage elements. The stored data can be changed by applying varying inputs. It is the basic storage element in sequential logic. the latch is level-triggered (outputs can change as soon as the inputs change) the flip flop is edge triggered (changes state when a control signal goes from high to low or low to high) 41 Latches and Flip Flops Falling edge Level change Level change Rising edge 42  Latches and Flip Flops clock Some input Some input Some output Some output 43  nor RS-Latch (level-triggered) 0 0 1 0 1 0 1 0 0 1 1 0 44