Computer Abstractions and Technology PDF

Computer Abstractions and Technology ❑ Cloud Computing refers to (1) large collection of The Computer Revolution servers that provide services over the internet, (2) dynamically varying numb...

Computer Abstractions and Technology ❑ Cloud Computing refers to (1) large collection of The Computer Revolution servers that provide services over the internet, (2) dynamically varying number of servers as a utility. ✓ Progress in computer technology Understanding Performance ✓ Underpinned by Moore’s Law ❑ Algorithm ✓ Makes novel applications feasible ❑ Determines number of operations executed ✓ Computers in automobiles ❑ Programming Language, Compiler, Architecture ✓ Cell phones ❑ Determine number of machine instructions executed ✓ Computers are pervasive per operation Classes of Computers ❑ Processor and Memory System ❑ Personal Computers ❑ Determine how fast instructions are executed ❑ General purpose, variety of software ❑ I/O System (Including OS) ❑ Subject to cost/performance tradeoff Eight Great Ideas ❑ Server Computers ❑ Design for Moore’s Law ❑ Network based ❑ Use abstraction to simplify designi67 ❑ High capacity, performance reliability ❑ Make the common case fast ❑ Range from small servers to building sized ❑ Performance via parallelism ❑ Super Computers ❑ Performance via pipelining ❑ High—end scientific and engineering ❑ Performance via prediction calculations ❑ Hierarchy of memories ❑ Highest capability but represent a small fraction ❑ Dependability via redundancy of the overall computer market Below Your Program ❑ Embedded Computers ❑ Application software ❑ Hidden as components of systems ❑ Written in high-level language ❑ Stringent power/performance/cost constraints ❑ System Software Post PC Era ❑ Compiler: translates HLL code to machine code ❑ Personal Mobile Device (PMD) ❑ Operating system ❑ Battery Operated ❑ Hardware’s ❑ Connects to the Internet ❑ Processor, memory, I/O controllers ❑ Cloud Computing Levels of Program Code ❑ Warehouse Scale Computers (WSC) ❑ High—Level Language ❑ Software as a Service (SaaS) like Web search, social networking ❑ Level of abstraction closer to problem domain Cloud Computing  ❑ Provides for productivity and portability ❑ An x86 processor and an ARM processor have different ISAs, but each defines how to perform ❑ Assembly Languages operations like addition, subtraction, memory access, etc. ❑ Textual representation of instructions ❑ Application binary interface ❑ Hardware Representation ❑ It extends the ISA to define how programs ❑ Binary digits (bits) interface with the operating system and other software ❑ Encoded instructions and data components. Inside the Processor (CPU) ❑ Ensures that compiled software can run on different systems with the same ISA and operating ❑ Datapath: performs operations on data system. ❑ Control: sequences Datapath, memory,… The switch form Uniprocessor to Multiprocessors ❑ Cache Memory: What is a Uniprocessor System ❑ Small fast SRAM (Static Random Access ❑ A uniprocessor system has a single Central Memory) memory form immediate access of data. Processing Unit (CPU) that performs all computational tasks. ❑ SRAM: It retains data as long as power is supplied, but the data is lost when ❑ It has a simpler design and control. ❑ Cache Memory: It acts as a buffer between a slower ❑ Limited to executing one instruction stream at a storage layer (such as RAM or a hard drive) and a time. faster processing unit (such as a CPU or GPU). The ❑ Performance improvements rely on increasing the primary purpose of a cache is to reduce the time and clock speed or optimizing instruction execution (e.g., energy required to access data by keeping commonly pipelining, caching). used information readily available. What is a Multiprocessor System? Abstractions ❑ A multiprocessor system has two or more CPUs ❑ Abstraction in microprocessors is a fundamental (also called cores) working together to execute tasks. concept that simplifies the complexity of designing and programming these systems. ❑ Having parallel execution of instructions. ❑ It allows engineers and developers to focus on ❑ Shared or distributed memory systems. specific levels of functionality without needing to understand every detail of the underlying hardware. ❑ Improved performance through task division and load balancing. ❑ It helps us deal with complexity ❑ A multiprocessor system is a collection of a number ❑ Abstraction layers break down this complexity into of standard processors but together in an innovative manageable parts, enabling designers to work at way to improve the performance/speed of computer different levels without needing to understand every hardware. detail of the hardware. Processor Coupling ❑ Instruction Set Architecture (ISA) ❑ Multiprocessor systems have more than one ❑ The ISA is the set of instructions that a processing unit sharing memory/peripheral devices. microprocessor can execute, defining its They have greater computing power, and higher hardware/software interface. reliability. ❑ It provides a standard interface for programmers Classification of Multiprocessor: to write software, abstracting the details of the ❑ Tightly-Coupled hardware implementation. ❑ Loosely-Coupled components within a single system, like a motherboard in a computer. ❑ Components are connected but operate Tightly-Coupled independently, with ❑ Each processor is assigned a specific duty but communication happening over a network or bus. processors work in close association, possibly sharing one memory module. Bus – a bus works in DATA LINES – carry actual data being transferred, ❑ Tightly-coupled multiprocessor systems contain multiple CPUs that are connected at the bus level. ADDRESS LINES – indicates the location in memory or to a device where data is to be read from or written ❑ Components are closely connected and work to, CONTROL LINES – handles the coordination of together in a unified Manner. the data transfer, ensuring that data is sent at the right time and in the right order. ❑ Sharing memory – processors or components share the same memory space, making communication ❑ Components are connected but operate between them faster. independently, with communication happening over a network or bus. ❑ His Interdependence (the state of being dependent upon one another) - Types of Buses: The components are highly dependent on each other System Bus - A common bus that connects the for operations. CPU, memory, and other components within the computer. ❑ Centralized Controls – Usually managed by a single controller or operating system. Peripheral Bus - Used to connect external devices (like printers, storage devices, etc.) to the system. Loosely-Coupled Backplane Bus - found in servers and high- ❑ Components are connected but operate performance systems, it connects multiple boards (with independently, with communication happening over a processors and memory) to communicate in a modular network or bus. system. Network – a system of connected devices or ❑ Components are connected but operate computers that communicate with each other over a independently, with communication happening over a medium. network or bus. In a cloud computing system, multiple servers are ❑ Each processor or component has its own memory, connected via a network. and communication occurs via messages or data Each server handles different tasks and communicates exchange. over the network to share data or results, but each server can operate independently, and adding more ❑ Lower Interdependence – components can work on servers for additional load is straightforward. their own without relying heavily on others. ❑ Components are connected but operate ❑ Each component may operate with its own control independently, with communication happening over a logic. network or bus. Multiprocessor Interconnections Bus – a communication pathway or system that ❑ Bus-Oriented System allows different components within a computer to exchange data. ❑ Crossbar-connected System A bus is used to connect components so they can ❑ Hyper Cubes send and receive data. Unlike networks that can span large distances, a bus is typically used for connecting ❑ Multistage Switch-based System  ❑ Cache with Shared Memory ❑ Bus-Oriented System is a way to connect multiple processors (or CPUs) and memory units in a multiprocessor system using a shared communication bus. The bus acts like a common "highway" for data transfer between all components. Processors and memory are connected by a common bus. Communication between processors (P1, P2, P3 and P4) and with globally shared memory is possible ❑ Crossbar-Connected System over a shared bus. It is a grid structure of processor and memory ❑ Bus-Oriented System: PROBLEM modules. The problem of CONTENTION (when two or more A grid of switches connects every processor to devices are enabled on. a bus at the same time and every memory unit directly. attempt to drive the bus to opposite logic values.) at Each processor has its own dedicated path to access two points, one is shared bus and the other is shared memory, avoiding conflicts. memory. ❑ Cache with Shared Memory Cache along with the Shared Memory Cache associated with each individual processor. ❑ CACHE It acts as a buffer between the processor and the main memory, storing the most commonly or recently used data and instructions. Every cross point of grid structure is attached with switch. In order to work with cache, first it checks the cache to see if the data is already there (a cache hit). If A simultaneous access between processor and the data is not in the cache (a cache miss), it retrieves memory modules as N numbers of processors are the data from the slower main memory and stores a provided with N number of memory modules. copy in the cache for future use. Crossbar needs N^2 switches for fully connected ❑ Types of CACHE network between processors and memory.. L1 Cache (LEVEL 1) Processors may or may not have their private memories. L2 Cache (LEVEL 2) ❑ Hypercubes System L3 Cache (LEVEL 3)  Processors are arranged in a cube-like structure, with each processor connected to a set of neighbors. The number of connections for each processor depends on the dimensionality of the cube. Data is routed through intermediate processors if direct communication is not possible. This architecture has some advantages over other architectures of multiprocessing system. In an n-degree hypercube architecture, we have: 2^n nodes (total number of processors) Nodes are arranged in n-dimensional cube, each node is connected to n number of nodes. This architecture has some advantages over other architectures of multiprocessing system. In an n-degree hypercube architecture, we have: The adjacent nodes (n-1) are differing in 1 bit and the nth node is having maximum ‘n’ inter-node distance. 3-degree hypercube will have 2^n nodes – 2^3 = 8 nodes Nodes are arranged in 3-dimensional cube, that is each node is connected to 3 no. of nodes. Each node is assigned with a unique address, which lies between 0 to 7 (2^n -1) ; 000, 001, 010,011,100,101,110,111 ❑ Multistage Switch-based System It permits simultaneous connection between several input output pairs. It consists of several stages of switches which provide multistage interconnection network. Uses multiple layers of switches to connect processors and memory units. Each layer routes data closer to its destination. Module 2: Instructions: Language of the Computer  Regularity makes implementation simpler  Simplicity enables higher performance at lower MIPS Instruction Set Architecture cost Instruction Set Arithmetic Instructions  Set of instructions supported by a machine C code:  Specific to a machine f = (a+b)*(c-d);  It follows a similar format.  Earlier computers used to have small and simple Compiled Mips code: instruction sets. add t0, a, b #temp t0 = a+b  Many modern computers also have simple sub t1, c, d #temp t1 = c-d instruction sets. mul f, t0, t1 #f = t0 * t1 Instruction Set Architecture  Usually defines a “family” of microprocessors.  Examples: Intel x86 (IA32), Sun Sparc, DEC Alpha, IBM/360, IBM PowerPC, M68K, DEC VAX.  Formally, defines the interface between a user and a microprocessor.  It includes instruction set  Rules for using instructions  Mnemonics (symbolic codes that represent machine language instructions.), functionality, addressing modes.  Instruction encoding  In terms of abstractions, it is a low-level detail of microprocessor that is “invisible” to user. Register Operands MIPS (Million Instructions per Second)  it refers to the processor registers as the source or  In another term, it is a way to estimate how fast a destination of data during the execution of machine computer processes information. instructions.  However, comparing these numbers can be tricky because of different measurement methods and the  In computer architecture, registers are small, fast types of instructions used by different computers storage locations within the CPU that can be can lead to misleading results. directly accessed by the processor.  To break it even better, it is like trying to compare two cars’ speed when they have different  Arithmetic instructions use register operandsMIPS speedometers and use different types of fuel thus it has 32 registers, numbered from 0 to 31Each can be challenging to get a clear and fair register is 32 bit long (word). comparison.  Design Principle Design Principle 2: Smaller is faster Arithmetic Instructions Registers are small but faster than memory  Add instruction: add two operands (a = b + c)  Two source operands (b and c) and one destination Register Number and Name Mapping operand (a)add a,b,c  Add 3 operands ( a = b + c + d)  Register 0 is the zero register ($zero) has a fixed  add c, c, d #c = c + d value of 0.  add a,b,c #a = b + c  2 Value registers  All arithmetic operations are performed in this  Register 2 and register 3, denoted by $v0 and $v1 manner respectively  10 temporary registers Design Principle Design Principle 1: Simplicity favors  Register 8 to register 15, denoted by $t0 - $t7. regularity  Register 24 and register 25, denoted by $t8 and $t9 respectively.  8 save register Design Principle  Register 16 to register 23, denoted by $s0 - $s7  Register 28 is the global pointer for static data Design Principle 3: Make the common case fast denote by $gp.  Register 29 is the stack pointed denote by $sp  Small constants are common  Register 30 is the frame pointer denote by  Immediate operand avoids a load instruction Use of Register Constant Zero C code: f = (a+b)*(c-d); In MIPS, register 0 ($zero) has a constant 0. Cannot be overwritten Compiled MIPS code: Add $zero, $zero, 2 save f, a,b,c,d in $s0, $s1, $s2, $s3, $s4 respectively. Example: add $t0, $s1, $s2#temp t0 = a + b sub $t1, $s3, $s4#temp t1 = c – d mov $t2, $s1 #$t2