CSC 204 Assembly Language - Chapter 02 - Fall 2024 - PDF

Assembly Language Programming Chapter 02 Rabih Tarraf x86 Processor Architecture Topics General Concept...

Assembly Language Programming Chapter 02 Rabih Tarraf x86 Processor Architecture Topics General Concepts 2.3.1 64-Bit Operation Modes 2.1.1 Basic Microcomputer Design 2.3.2 Basic 64-Bit Execution 2.1.2 Instruction Execution Cycle Environment 2.1.3 Reading from Memory Components of a Typical x86 2.1.4 Loading and Executing a Computer Program 2.4.1 Motherboard 32-Bit x86 Processors 2.4.2 Memory 2.2.1 Modes of Operation 2.4.3 Section Review 2.2.2 Basic Execution Environment 2.5 Input-Output System 2.2.3 x86 Memory Management 2.5.1 Levels of I/O Access 64-Bit x86-64 Processors rabih@tarraf 2 1  Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 3 General Concepts Basic microcomputer design Instruction execution cycle Reading from memory How programs run rabih@tarraf 4 2 The Block Diagram of a microprocessor- based computer system rabih@tarraf 5 Basic Microcomputer Design The central processor unit (CPU), where data bus calculations and logical operations take place, contains a limited number of storage locations named registers, a high-frequency clock, a control registers unit, and an arithmetic logic unit. Central Processor Unit Memory Storage I/O I/O Device Device The clock synchronizes the internal operations of the (CPU) Unit #1 #2 CPU with other system components. ALU CU clock The control unit (CU) coordinates the sequencing of steps involved in executing machine instructions. control bus The arithmetic logic unit (ALU) performs arithmetic address bus operations such as addition and subtraction and logical operations such as AND, OR, and NOT. rabih@tarraf 6 3  Clock Clock Each operation involving the CPU and the system bus is synchronized by an internal clock pulsing at a constant rate. The basic one cycle unit of time for machine instructions is a machine cycle (or clock cycle). 1 The length of a clock cycle is the time required for one complete clock pulse. In the following figure, a clock cycle is depicted as the time between 0 one falling edge and the next: The duration of a clock cycle is calculated as the reciprocal of the clock’s speed, which in turn is measured in oscillations per second. A clock that oscillates 1 billion times per second (1 GHz), for example, produces a clock cycle with a duration of one billionth of a second (1 nanosecond). A machine instruction requires at least one clock cycle to execute, and a few require in excess of 50 clocks (the multiply instruction on the 8088 processor, for example). Instructions requiring memory access often have empty clock cycles called wait states because of the differences in the speeds of the CPU, the system bus, and memory circuits. rabih@tarraf 7 Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 8 4  Instruction Execution Cycle Fetch Decode Fetch operands Execute Store output rabih@tarraf 9 How does a CPU work? rabih@tarraf 10 5  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000000 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 INSTRUCTION 5 00000000 CONTROL REGISTER 6 00000000 UNIT RAM 0000 0000 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address 10 00000000 00000000 Input 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 11 …. …. Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000000 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0000 0000 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address 10 00000000 00000000 Input 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00010001 14 00000011 Write Enable 15 00001110 rabih@tarraf 12 …. …. 6  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000000 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0000 0000 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags 10 00000000 00000000 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00010001 14 00000011 Write Enable 15 00001110 rabih@tarraf 13 …. …. Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000000 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0010 1110 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address 10 00000000 00000000 Input 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00010001 14 00000011 Write Enable 15 00001110 rabih@tarraf 14 …. …. 7  CHECK IF LOAD-A Instruction rabih@tarraf 15 Instruction Table ADDRESS OR INSTRUCTION DESCRIPTION 4 –BIT OPCODE REGISTERS Read RAM location into LOAD-A register A 0010 4-BIT RAM address Read RAM location into LOAD-B register B 0001 4-BIT RAM address Write from register A into STORE-A RAM location 0100 4-BIT RAM address Add two registers, store 2-bit register ID, ADD result into second register 1000 2-bit register ID rabih@tarraf 16 8  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000000 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0010 1110 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address 10 00000000 00000000 Input 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 17 …. …. Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000011 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 Write Enable 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0010 1110 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address 10 00000000 00000000 Input 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 18 …. …. 9  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000011 00000000 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0001 1111 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address Input 10 00000000 00000001 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 19 …. …. Instruction Table ADDRESS OR INSTRUCTION DESCRIPTION 4 –BIT OPCODE REGISTERS Read RAM location into LOAD-A register A 0010 4-BIT RAM address Read RAM location into LOAD-B register B 0001 4-BIT RAM address Write from register A into STORE-A RAM location 0100 4-BIT RAM address Add two registers, store 2-bit register ID, ADD result into second register 1000 2-bit register ID rabih@tarraf 20 10  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000011 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0001 1111 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address Input 10 00000000 00000001 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 21 …. …. Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000011 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 1000 0100 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address Input 10 00000000 00000010 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 22 …. …. 11  Instruction Table ADDRESS OR INSTRUCTION DESCRIPTION 4 –BIT OPCODE REGISTERS Read RAM location into LOAD-A register A 0010 4-BIT RAM address Read RAM location into LOAD-B register B 0001 4-BIT RAM address Write from register A into STORE-A RAM location 0100 4-BIT RAM address Add two registers, store 2-bit register ID, ADD result into second register 1000 2-bit register ID rabih@tarraf 23 Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00000011 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 1000 0100 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address Input 10 00000000 00000010 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 24 …. …. 12  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00010001 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 1000 0100 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Flags Address Input 10 00000000 00000010 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 25 …. …. Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00010001 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0100 1101 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Address Flags Input 10 00000000 00000011 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 26 …. …. 13  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00010001 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0100 1101 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Address Flags Input 10 00000000 00000011 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00000000 14 00000011 Write Enable 15 00001110 rabih@tarraf 27 …. …. Instruction Table ADDRESS OR INSTRUCTION DESCRIPTION 4 –BIT OPCODE REGISTERS Read RAM location into LOAD-A register A 0010 4-BIT RAM address Read RAM location into LOAD-B register B 0001 4-BIT RAM address Write from register A into STORE-A RAM location 0100 4-BIT RAM address Add two registers, store 2-bit register ID, ADD result into second register 1000 2-bit register ID rabih@tarraf 28 14  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 00101110 00010001 00001110 00000000 00000000 1 00011111 2 10000100 3 01001101 4 00000000 5 00000000 CONTROL INSTRUCTION REGISTER 6 00000000 UNIT RAM 0100 1101 7 00000000 (OPCODE) 8 00000000 0 Z N 9 00000000 Address Flags Input 10 00000000 00000011 11 00000000 INST. ADDR. REGISTER 12 00000000 READ Enable 13 00010001 14 00000011 Write Enable 15 00001110 rabih@tarraf 29 …. …. More Instructions Examples 15  Instruction Table INSTRUCTION DESCRIPTION ADDRESS OR REGISTERS LOAD-A Read RAM location into register A 4-BIT RAM address LOAD-B Read RAM location into register B 4-BIT RAM address STORE-A Write from register A into RAM location 4-BIT RAM address 2-bit register ID, ADD Add two registers, store result into second register 2-bit register ID Subtract two registers, store value into second 2-bit register ID, SUB register 2-bit register ID Update instruction address register to new address JUMP (i.e. jump to address) 4-bit memory address If ALU result was negative, update instruction JUMP-NEG address register to new address 4-bit memory address HALT Program done. Halt computer NA rabih@tarraf 31 Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 LOAD_A 14 1 LOAD_B 15 0 0 0 0 2 ADD B A 3 STORE_A 13 4 JUMP2 5 HALT CONTROL INSTRUCTION REGISTER 6 0 UNIT RAM 0 7 0 8 0 (OPCODE) 0 Z N 9 0 Flags 10 0 0 11 0 INST. ADDR. REGISTER 12 0 READ 13 0 Enable 14 1 Write Enable 15 1 rabih@tarraf …. …. 32 16  Data Address Data REGISTER A REGISTER B REGISTER C REGISTER D 0 LOAD_A 14 1 LOAD_B 15 0 0 0 0 2 SUB A B 3 JUMP_NEG 5 4 JUMP 2 5 ADD B A CONTROL INSTRUCTION REGISTER 6 STORE_A 13 UNIT RAM 0 7 HALT 8 0 (OPCODE) 0 Z N 9 0 Flags 10 0 0 11 0 INST. ADDR. REGISTER 12 0 READ 13 0 Enable 14 12 Write Enable 15 7 rabih@tarraf …. …. 33 INTEL 4004 CPU rabih@tarraf 34 17  Reading from Memory Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: 1. Place the address of the value you want to read on the address bus. 2. Assert (changing the value of) the processor’s RD (read) pin. 3. Wait one clock cycle for the memory chips to respond. 4. Copy the data from the data bus into the destination operand rabih@tarraf 35 Cache Memory High-speed expensive static RAM both inside and outside the CPU. Level-1 cache: inside the CPU Level-2 cache: outside the CPU Cache hit: when data to be read is already in cache memory Cache miss: when data to be read is not in cache memory. rabih@tarraf 36 18  How a Program Runs rabih@tarraf 37 32-Bit x86 Processors 19  IA-32 Processor Architecture Modes of operation Basic execution environment Floating-point unit Intel Microprocessor history rabih@tarraf 39 Addressable Memory Protected mode 4 GB 32-bit address Real-address and Virtual-8086 modes 1 MB space 20-bit address rabih@tarraf 40 20  Modes of Operation Protected mode (4GB) Native mode (windows, linux) All instructions and features are available. Programs are given separate memory areas named segments, and the processor prevents programs from referencing memory outside their assigned segments. Real-address mode (1 MB) Native MS-DOS Implements the programming environment of an early intel processor with a few extra features, such as the ability to switch into other modes. This mode is useful if a program requires direct access to system memory and hardware devices. System management mode Power management, system security, diagnostics Virtual-8086 mode The computer runs in protected mode and creates a virtual-8086 machine with its own 1-mbyte Hybrid of protected Each program has its own 80x86 computer (windows NT, 2000, and XP) rabih@tarraf 41 Basic Execution Environment Addressable memory General-purpose registers Index and base registers Specialized register uses Status flags Floating-point, MMX, XMM registers rabih@tarraf 42 21 Internal microprocessor architecture Accumulator Base index loop counter Data holds a part of the result from a multiplication or part of the dividend before a division rabih@tarraf 43 Internal microprocessor architecture rabih@tarraf 44 22  Internal microprocessor architecture rabih@tarraf 45 Accessing Parts of Registers Use 8-bit name, 16-bit name, or 32-bit name Applies to EAX, EBX, ECX, and EDX 8 8 AH AL 8 bits + 8 bits AX 16 bits EAX 32 bits EAX : used by multiplication and division instructions. Called Extended accumulator register. The CPU automatically uses ECX as a loop counter. rabih@tarraf 46 23  General-Purpose Registers Named storage locations inside the CPU, optimized for speed. 32-bit General-Purpose Registers EAX EBP Eight general- EBX ESP purpose registers ECX ESI EDX EDI 16-bit Segment Registers EFLAGS CS ES Processor status flags register (EFLAGS) SS FS Six segment Instruction pointer (EIP) EIP registers DS GS rabih@tarraf 47 Some Specialized Register Uses (1 of 2) General-Purpose EAX – accumulator ECX – loop counter ESP – stack pointer ESI, EDI – index registers EBP – extended frame pointer (stack) Segment CS - points at the segment containing the current program. DS - generally points at segment where variables are defined. SS - points at the segment containing the stack. ES - extra segment register, it’s up to a coder to define its usage. ES is used as a temporary segment register ES, FS, GS - additional segments rabih@tarraf 48 24  General Purpose Regsiter 8086 CPU has 8 general purpose registers, each register has its own name: AX - the accumulator register (divided into AH / AL). BX - the base address register (divided into BH / BL). CX - the count register (divided into CH / CL). DX - the data register (divided into DH / DL). SI - source index register. DI - destination index register. They are often used as pointers, but can be used for many of the same purposes as the general registers BP - base pointer. SP - stack pointer. point to data in the machine language stack rabih@tarraf 49 Index and Base Registers Some registers have only a 16- ESP addresses data on the stack (a system memory structure). It is bit name for their lower half: rarely used for ordinary arithmetic or data transfer. It is often called the extended stack pointer register. ESI and EDI are used by high-speed memory transfer instructions. They are sometimes called the extended source index and extended destination index registers. EBP is used by high-level languages to reference function parameters and local variables on the stack. It should not be used for ordinary arithmetic or data transfer except at an advanced level of programming. It is often called the extended frame pointer register. rabih@tarraf 50 25  Some Specialized Register Uses (2 of 2) EIP – instruction pointer Register contains the address of the next instruction to be executed. Certain machine instructions manipulate EIP, causing the program to branch to a new location. EFLAGS status and control flags each flag is a single binary bit rabih@tarraf 51 The EFLAG and FLAG register counts for the entire X86 and Pentium microprocessor family. rabih@tarraf 52 26  Status Flags Carry unsigned arithmetic out of range Overflow signed arithmetic out of range Sign result is negative Zero result is zero Auxiliary Carry carry from bit 3 to bit 4 Parity sum of 1 bits is an even number rabih@tarraf 53 Special Purpose Register IP - the instruction pointer. IP register always works together with CS segment register and it points to currently executing instruction. Flags Register - determines the current state of the processor. Flags Register is modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. Generally you cannot access these registers directly. rabih@tarraf 54 27  Floating-Point, MMX, XMM Registers Eight 80-bit floating-point data registers ST(0), ST(1),... , ST(7) arranged in a stack used for all floating-point arithmetic Eight 64-bit MMX registers Eight 128-bit XMM registers for single- instruction multiple-data (SIMD) operations rabih@tarraf 55 Multipurpose Registers RAX is referenced as a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of two 8-bit registers (AH and AL). Note that if an 8- or 16-bit register is addressed, only that portion of the 32- bit register changes without affecting the remaining bits. The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions. For these instructions, the accumulator has a special purpose, but is generally considered to be a multipurpose register. In the 80386 and above, the EAX register may also hold the offset address of a location in the memory system. In the 64-bit Pentium 4 and Core2, RAX holds a 64-bit offset address, which allows 1T (terra) byte of memory to be accessed through a 40-bit address bus. In the future, Intel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory. rabih@tarraf 56 28  Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 57 IA-32 Memory Management Real-address mode Calculating linear addresses Protected mode Multi-segment model Paging rabih@tarraf 58 29  Protected Mode (1 of 2) 4 GB addressable RAM (00000000 to FFFFFFFFh) Each program assigned a memory partition which is protected from other programs Designed for multitasking Supported by Linux & MS-Windows rabih@tarraf 59 Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 60 30  64-Bit x86 Processors 64-Bit Processors 64-Bit Operation Modes Compatibility mode – can run existing 16-bit and 32-bit applications (Windows supports only 32-bit apps in this mode) 64-bit mode – Windows 64 uses this Basic Execution Environment addresses can be 64 bits (48 bits, in practice) 16 64-bit general purpose registers 64-bit instruction pointer named RIP rabih@tarraf 62 31  64-Bit General Purpose Registers 32-bit general purpose registers: EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D 64-bit general purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9, R10, R11, R12, R13, R14, R15 rabih@tarraf 63 32bit and 64bit Registers 32 bit register start with reg. eax, ebx 64 bit register start with reg. rax, rbx rabih@tarraf 64 32  Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 65 Components of an IA-32 Microcomputer Motherboard Video output Memory Input-output ports rabih@tarraf 66 33  Motherboard CPU socket External cache memory slots Main memory slots BIOS chips Sound synthesizer chip (optional) Video controller chip (optional) IDE, parallel, serial, USB, video, keyboard, joystick, network, and mouse connectors PCI bus connectors (expansion cards) rabih@tarraf 67 Intel D850MD Motherboard mouse, keyboard, parallel, serial, and USB Video connectors Audio chip PCI slots memory controller hub Pentium 4 socket AGP slot dynamic RAM Firmware hub I/O Controller Speaker Power connector Battery Diskette connector Source: Intel® Desktop Board D850MD/D850MV Technical Product IDE drive connectors Specification rabih@tarraf 68 34  Intel 965 Express Chipset rabih@tarraf 69 Video Output Video controller on motherboard, or on expansion card AGP (accelerated graphics port technology)* Video memory (VRAM) Video CRT Display uses raster scanning horizontal retrace vertical retrace Direct digital LCD monitors no raster scanning required Sample Video Controller (ATI Corp.) * This link may change over time. rabih@tarraf 70 35  Main Components of Computer rabih@tarraf 71 Memory ROM read-only memory EPROM erasable programmable read-only memory Dynamic RAM (DRAM) inexpensive; must be refreshed constantly Static RAM (SRAM) expensive; used for cache memory; no refresh required Video RAM (VRAM) dual ported; optimized for constant video refresh CMOS RAM complimentary metal-oxide semiconductor system setup information See: Intel platform memory (Intel technology brief: link address may change) rabih@tarraf 72 36  Input-Output Ports USB (universal serial bus) intelligent high-speed connection to devices up to 12 megabits/second USB hub connects multiple devices enumeration: computer queries devices supports hot connections Parallel short cable, high speed common for printers bidirectional, parallel data transfer Intel 8255 controller chip rabih@tarraf 73 Input-Output Ports (cont) Serial RS-232 serial port one bit at a time uses long cables and modems 16550 UART (universal asynchronous receiver transmitter) programmable in assembly language rabih@tarraf 74 37  Device Interfaces ATA host adapters intelligent drive electronics (hard drive, CDROM) SATA (Serial ATA) inexpensive, fast, bidirectional FireWire high speed (800 MB/sec), many devices at once Bluetooth small amounts of data, short distances, low power usage Wi-Fi (wireless Ethernet) IEEE 802.11 standard, faster than Bluetooth rabih@tarraf 75 Chapter Overview Components of General IA-32 Processor IA-32 Memory 64-bit Input-Output an IA-32 Concepts Architecture Management Processors System Microcomputer rabih@tarraf 76 38  Levels of Input-Output Level 3: High-level language function examples: C++, Java portable, convenient, not always the fastest Level 2: Operating system Application Programming Interface (API) extended capabilities, lots of details to master Level 1: BIOS drivers that communicate directly with devices OS security may prevent application-level code from working at this level rabih@tarraf 77 Displaying a String of Characters Application Program Level 3 When a HLL program displays a string of characters, the following steps take place: OS Function Level 2 BIOS Function Level 1 Hardware Level 0 rabih@tarraf 78 39  Programming levels Assembly language programs can perform input-output at each of the following levels: rabih@tarraf 79 Intel x86-64 Architecture rabih@tarraf 80 40  Intel x86-64 Architecture rabih@tarraf 81 Summary Central Processing Unit (CPU) Arithmetic Logic Unit (ALU) Instruction execution cycle Multitasking Floating Point Unit (FPU) Complex Instruction Set Real mode and Protected mode Motherboard components Memory types Input/Output and access levels rabih@tarraf 82 41 Chapter rabih@tarraf 83 Good Reference rabih@tarraf 84 42