Computer & Interfacing Chapter 2 PDF

Chapter Two. The 8086 Microprocessor Architecture microprocessor and assembly language 1  Outline of the chapter  Features of 8086  Architecture of 8086  Register Organization  Bus Operation  Memory Segmentatio...

Chapter Two. The 8086 Microprocessor Architecture microprocessor and assembly language 1  Outline of the chapter  Features of 8086  Architecture of 8086  Register Organization  Bus Operation  Memory Segmentation  Features of 8086 1. The 8086 is a 16-bit microprocessor.  The term "16-bit" means that its ALU, internal registers and most of its instructions are designed to work with16-bit binary words. 2. The 8086 has a 16-bit data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time. 3. The 8086 has a 20-bit address bus, so it can directly access 220 or 1,048,576 (1Mb) memory locations.  Each of the 1,048,576 memory locations is byte wide.  Therefore, a 16 bit words are stored in two consecutive memory locations. 4. The 8086 can generate 16-bit I/O address, hence it can access 216 ~ 65536 I/O ports. 5. The 8086 provides fourteen 16-bit registers.  Features of 8086 6. The 8086 has multiplexed address and data bus which reduces the number of pins needed, but does slow down the transfer of data (drawback). 7. The 8086 requires one phase clock with a 33% duty cycle to provide optimized internal timing. 8. It is possible to perform bit, byte, word and block operations in 8086.  It performs the arithmetic and logic operations on bit, byte, word and decimal numbers including multiply and divide.  Features of 8086 9. The Intel 8086 is designed to operate in two modes, namely  The minimum mode and  The maximum mode. Min.= Control signals are issues by CPU,  Max.= Control signals are issued by external bus controller (8288). 10. The Intel 8086 supports multiprogramming.  In multiprogramming, the code for two or more processes is in memory at the same time and is executed in a time-multiplexed fashion. 11. Intel 8086 has 6 bytes instruction cache or queue. 12. The 8086 provides powerful instruction set with different addressing modes such as:-  Register, immediate, direct, indirect through an index or base, indirect through the sum of a base and an index register, relative and implied.  Architecture of 8086  The simplified block diagram of the 8086 processor model is organized as two separate processors :  Bus Interface Unit (BIU)  Execution Unit (EU).  The bus interface unit is responsible for performing all external bus operations.  The execution unit tells the BIU from where to fetch instructions or data, decodes instructions and executes instructions.  These two functional units(BIU & EU) can work simultaneously to increase system speed and hence the No. of instruction per second.  Block Diagram Architecture  BIU: Is the 8086’s interface to the outside world and provides a full 16-bit bi-directional data bus and 20-bit address bus.  Function of BIU:  Sends address of the memory or I/O,  Fetches instruction from memory,  Reads/writes data from/into port/memory,  Supports instruction queuing and  Provides the address relocation facility  To implement these functions; the BIU contains:-  The instruction queue,  Segment registers,  Instruction pointer,  Address summer and  Bus control logic.  Architecture of 8086  INSTRUCTION QUEUE:  The main linkage between the two functional blocks is the instruction queue.  To speed up program execution, BIU fetches six instruction bytes ahead of time from the memory and holds for the EU in a group of registers called Queue.  Queue makes possible to fetch next instruction when current instruction is in execution.  Fetching the next instruction while the current instruction executes is called pipelining.  Architecture of 8086  EXECUTION UNIT (EU):- The EU of 8086:- Tells the BIU from where to fetch instructions or data. Decodes instructions and Executes instructions. It contains:  Control circuitry  Instruction decoder  ALU  Register Organization  Flag register  General purpose register  Pointers and  Index registers  Architecture of 8086  Control Circuitry, Instruction Decoder, ALU: The control circuitry in the EU directs the internal operations. A decoder in the EU translates the instructions fetched from memory into a ,series of actions which the EU performs. ALU is 16-bit. It can add, subtract, AND, OR, XOR increment, decrements, complement and shift binary numbers.  REGISTER ORGANIZATION  The 8086 has a powerful set of registers.  It includes:-  General purpose registers,  Segment registers,  Pointers and index registers, and  Flag register.  The fig 2.4 shows the register organization of 8086.  It is also known as programmer’s model of 8086.  The registers shown in programmer’s model are accessible to programmer.  All registers of 8086 are 16-bit registers.  Register Organization  GENERAL PURPOSE REGISTERS:  The 8086 has four 16-bit general purpose registers labeled AX, BX, CX and DX.  They are used for holding data, variables and intermediate results temporarily.  They can also be used as a counters or used for storing offset address for some particular addressing modes.  AX is used as 16-bit accumulator whereas AL is used as 8-bit accumulator.  BX is used as offset storage for generating physical addresses in case of certain addressing modes.  CX is used as a default counter in case of string and loop instructions.  SEGMENT REGISTERS  The physical address of the 8086 is 20-bit wide to access 1 Mbyte memory locations.  However, its registers and memory locations which contain logical addresses are just 16-bits wide.  8086 uses memory segmentation. It treats the 1 Mbyte of memory as divided into segments, with a maximum size of a segment as 64 Kbytes.  The 8086 allows only four active segments at a time, as shown in fig 2.5 and 16-bit segment registers are used for the selection.  These four segment registers are:  Code segment (CS) register,  The data segment (DS) register,  The stack segment (SS) register, and  The extra segment (ES) register.  Register Organization  SEGMENT REGISTERS:  Segment registers are used to hold the upper 16-bits of the starting addresses of the four memory segments, on which 8086 works at a time.  Starting address means the lowest addressed byte in the active segment. It is also known as base address or segment base.  The BIU always inserts zeros for the lower 4 bits in the contents of segment register to generate 20 bit base address.  Functions of segment registers:  CS register: holds the upper 16-bits of the starting address of the code segment.  SS register: holds the upper 16-bits of the starting address of the program stack segment.  ES and DS registers are used to hold the upper 16-bits of the starting address of the two memory segments which are used for data.  Register Organization  POINTERS AND INDEX REGISTERS The registers in this group are all 16 bits wide and, unlike the data registers, cannot be accessed as a low or high byte. These registers are used as memory pointers. Recall that all segment registers are 16-bit wide. But it is necessary to generate 20-bit address (physical address) on the address bus. To get 20-bit physical address one or more pointer or index registers are associated with each segment register. The pointer registers IP, and BP & SP are associated with code, and stack segments, respectively. The index registers DI & SI are used as a general purpose registers as well as for offset storage in some addressing modes.  Register Organization  FLAG REGISTER  A flag is a flip-flop which indicates some condition produced by the execution of an instruction or controls certain operations of the EU.  The flag register contains nine active flags as shown in the figure.  Six of them are used to indicate some condition produced by instruction.  FLAG REGISTER  CF: CARRY FLAG :-  Is set if there is a carry out of the MSB or used as borrow flag for subtraction (it is set when borrow is needed)  PF: PARITY FLAG :-  Is set if result of byte operation or lower byte of the word operation contain an even number of ones.  AF: AUXILIARY FLAG:-  Is set if there is an overflow out of bit 3 and is used for BCD operations.  ZF: ZERO FLAG:-  Is set if result of ALU is zero. And also if certain register content becomes zero following an increment or decrement operation.  SF: SIGN FLAG :-  Is set if MSB of the result is 1.  FLAG REGISTER  OF: OVERFLOW FLAG  Is set if result is out of range.  For addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice-versa.  For subtraction, it is set when the MSB needs a borrow and there is no borrow from the MSB, or vice versa bit 3 and is used for BCD operations.  Flag Register  The three remaining flags are used to control certain operations of the processor.  TF: Trap flag is used for single stepping through a program (for debugging).  If TF is set a trap is executed after execution of each instruction, i.e. interrupt service routine is executed which displays various registers and memory variable contents.  IF: Interrupt flag is used to allow/ prohibit the interruption of a program.  If set, a certain type of interrupt can be recognized by the 8086; otherwise these interrupts are ignored.  DF: direction flag is used with string instruction.  If DF = 0, the string is processed from its beginning with the first element having the lowest address.  Otherwise, the string is processed from the high address towards the low address. Examples on flags Quiz 2 [5%]  Memory Segmentation  Two types of memory organizations are commonly used:  Linear addressing &  Segmented addressing.  Linear Addressing:  Entire memory space is available to the processor in one linear array  Segmented addressing:  Available memory space is divided into segments.  A 1Mbytes of memory in Intel 8086 is divided into 4 logical segments with each 64 Kbytes in size.  Those separate segments are addressed by one of the segment registers;  16-bit contents of the segment register gives the starting/base address of a particular segment.  To address a specific memory location within a segment we need an offset address.  Offset address is also 16-bit wide and it is provided by one of the associated pointer or index register. Memory Segmentation  Memory Segmentation  Note that for memory segmentation: The four segments can overlap for small programs. In a minimum system all four segments can start at the address 00000H. The segment can begin/start at any memory address which is divisible by 10H.  Advantages of memory segmentation: 1. Allows the memory addressing capacity to be 1 Mbyte (though L.A is 16-bit) 2. Allows instruction code, data, and stack portion of program to be more than 64 KB long by using more than one code, data, stack segment, and extra segment. 3. Facilitates use of separate memory areas for program, data and stack. 4. Permits program relocation which is very useful in multiprogramming.  Generation of 20-bit address  GENERATION OF 20-BIT ADDRESS:  The Intel 8086 generates 20-bit physical address using the contents of segment register and the offset register associated with it.  Offset registers include:  Instruction pointer(IP): Contains the 16-bit offset from the code segment.  Stack pointer(SP): Contains the 16-bit offset from the segment to the top of stack. E.g. if SS =4000H and SP=9F20H, then Physical address = SS* 10H + SP = 40000H + 9F20H = 49F20H.  Base pointer(BP): Can be used instead of SP in different addressing mode.  Source Index(SI): Is used to hold the offset of a data word in the data segment.  Destination Index(DP): String instructions always use ES and DI to determine 20-bit physical address for the destination.  Logical address and physical address  In Intel literature concerning the 8086, there are three types of addresses mentioned frequently:  The physical address.  The offset address, and  The logical address.  The physical address is the 20-bit address that is actually put on the address pins of the 8086. This address can have a range of 00000H to FFFFFH for the 8086 CPU.  This is an actual physical location in RAM or ROM within the 1MB memory range.  The offset address is a location within a 64K-byte segment range. Therefore, an offset address can range from 0000H to FFFFH.  The logical address consists of a segment value and an offset address. LOGIGAL ADDRESS = SEGMENT VALUE : OFFSET VALUE  Logical address and physical address.  Logical address and physical address EXAMPLE:  ASSIGNMENT 1: 1. If CS = 3499H and IP= 2500H, find: a. The logical address b. The physical address c. The lower and upper ranges of the code segment 2. If DS = 3499H and the offset= 3FB9H, find: a. The physical address b. The logical address of the data being fetched c. The lower and upper range addresses of the data segment 3. If SS= 2000 and SP= 4578, find: a. The physical address b. The logical address c. The lower range of the stack segment d. The upper range of the stack segment EXAMPLES  EXAMPLES.  Memory Segmentation  Table 2.1 shows that some memory references and their default and alternate segment definitions.  For example, instruction codes can only be stored in the code segment with IP used as an offset.  Similarly, for stack operations only SS and SP or BP registers can be used to give segment and offset addresses respectively.  On the other hand, for accessing general data, string source, data pointed by BX and BP registers;  It is possible to use alternate segments by using segment override prefix. See examples given after Table 2.1. DEFAULT AND ALTERNATE REGISTER ASSIGNMENTS  Segment override prefix  Allows the programmer to deviate from the default segment.  The 80x86 CPU allows the program to override the default segment and use any segment register.  To do that, specify the segment in the code.  For example, in "MOV AL, [BX]", the physical address of the operand to be moved into AL is DS: BX, as was shown earlier since DS is the default segment for pointer BX.  To override that default, specify the desired segment in the instruction as "MOV AL, ES:[BX]".  Now the address of the operand being moved to AL is ES:BX instead of DS:BX.  Table 1-4 shows more examples of segment overrides shown next to the default address in the absence of the override.  Segment override prefix.