Computer Architecture - Introduction PDF

UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 1 Introduction...

UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 1 Introduction Instructor: Amna Al-Ojeli Architecture & Organization Architecture is those attributes visible to the programmer  Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques.  e.g. Is there a multiply instruction? Organization is how features are implemented  Control signals, interfaces, memory technology.  e.g. Is there a hardware multiply unit or is it done by repeated addition? Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition 1  Structure & Function Structure is the way in which components relate to each other Function is the operation of individual components as part of the structure Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition Functional View All computer functions are:  Data processing  Data storage  Data movement  Control Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition 2  Operations (a) Data movement The computer must be able to move data between itself and the outside world Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition Operations (b) Storage The computer must temporarily store at least those pieces of data that are being worked on at any given moment Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition 3  Operation (c) Processing from/to storage Example: Any number-crunching application that takes data from memory and stores the result back in memory. Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition Operation (d) Processing from storage to I/O The data may take a wide variety of forms, and the range of processing requirements is broad. Files of data are stored on the computer for subsequent retrieval and update. Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition 4  The Computer - Top Level Structure Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition The Processor The purpose of the processor (CPU) is to fetch and execute instructions. The CPU consists of the following components:  Arithmetic Logic Unit (ALU): performs calculations and logical decisions.  Control Unit: sends signals to control how data moves around the CPU.  Cache: provides fast access to frequently used instructions and data.  Registers:  Program Counter (PC)  Memory Address Register (MAR)  Memory Data Register (MDR)  Accumulator (ACC) Amna Al-Ojeli Chapter 1 William Stallings Computer Organization and Architecture 9th Edition 5  UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 2 Computer Evolution and Performance Instructor: Amna Al-Ojeli Von Neumann Machines An example of computer architecture and organization, which is used by modern computers as a reference. Von Neumann machines is a computer’s category based on Von Neumann architecture (stored- program concept).  Data and program stored in the same space (memory).  Thus, the machines it self can alter either its programs or its internal data. Amna Al-Ojeli Chapter 2 William Stallings Computer Organization and Architecture 9th Edition 6  Von Neumann Machines\ Cont. Stored Program concept Main memory storing programs\ instructions and data An arithmetic and logic unit (ALU) capable of operating on binary data Control unit interprets instructions from memory and executes them Input and output (I/O) equipment operated by the control unit At the Princeton Institute for Advanced Studies  The IAS computer Amna Al-Ojeli Chapter 2 Started 1946 - Finished 1952 William Stallings Computer Organization and Architecture 9th Edition Structure of Von Neumann Machine Amna Al-Ojeli Chapter 2 William Stallings Computer Organization and Architecture 9th Edition 7  Computer Registers Set of registers (storage in CPU)  Memory Buffer Register: Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.  Memory Address Register: Specifies the address in memory of the word to be written from or read into the MBR.  Instruction Register: Contains the 8-bit opcode instruction being executed. Amna Al-Ojeli Chapter 2 William Stallings Computer Organization and Architecture 9th Edition Computer Registers\ Cont. Set of registers (storage in CPU)  Instruction Buffer Register: Employed to hold temporarily the righthand instruction from a word in memory.  Program Counter: Contains the address of the next instruction-pair to be fetched from memory.  Accumulator: Employed to hold temporarily operands and results of ALU operations. Amna Al-Ojeli Chapter 2 William Stallings Computer Organization and Architecture 9th Edition 8  IBM Systems The major manufacturer of punched-card processing equipment 1953 - the 701  IBM’s first stored program computer  Scientific calculations 1955 - the 702  Business applications Amna Al-Ojeli Lead to 700/7000 series Chapter 2 William Stallings Computer Organization and Architecture 9th Edition Transistors Replaced vacuum tubes Smaller Cheaper Less heat dissipation Solid State device Made from Silicon (Sand) Invented 1947 at Bell Labs Second generation machines Amna Al-Ojeli Chapter 2 William Stallings Computer Organization and Architecture 9th Edition 9  Semiconductor Memory In the 1950s and 1960s, most computer memory was constructed from tiny rings of ferromagnetic material called a core In 1970, Fairchild produced the first relatively capacious semiconductor memory. This chip, about the size of a single core, could hold 256 bits of memory. Much faster than core Amna Al-Ojeli Chapter 2 Capacity approximately doubles each year William Stallings Computer Organization and Architecture 9th Edition Evolution of Intel Microprocessors A breakthrough was achieved in 1971, when Intel developed its 4004.  The first chip to contain all of the components of a CPU on a single chip  Can add two 4-bit numbers and can multiply only by repeated addition Followed by 8008 in 1972  Was the first 8-bit microprocessor and was almost Amna Al-Ojeli twice as complex as the 4004. Chapter 2  Both designed for specific applications William Stallings Computer Organization and Architecture 9th Edition 10  Evolution of Intel Microprocessors Followed by 8080 in1974  Intel’s first general purpose microprocessor with 8- bit 8086 at the end of the 1970s  16-bit microprocessors began to be developed 80386 in 1985 Amna Al-Ojeli  Intel introduced its own 32-bit microprocessor Chapter 2 William Stallings Computer Organization and Architecture 9th Edition Speeding it up Branch prediction  The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next. Data flow analysis  The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions. Speculative execution  Using branch prediction and data flow analysis, some processors speculatively execute instructions ahead of Amna Al-Ojeli their actual appearance in the program execution, holding Chapter 2 the results in temporary locations. William Stallings Computer Organization and Architecture 9th Edition 11  UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 3 Computer Function Interconnection Instructor: Amna Al-Ojeli What is a program ? A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 12  Function of Control Unit For each operation a unique code is provided  e.g. ADD, MOVE A hardware segment accepts the code and issues the control signals Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out  Input/output Temporary storage of code and results is needed  Main memory Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 13  Instruction Cycle Two steps:  Fetch  Execute Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC  Unless told otherwise Instruction loaded into Instruction Register (IR) Amna Al-Ojeli Processor interprets instruction and performs required actions Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 14  Execute Cycle Processor-memory  data transfer between CPU and main memory Processor I/O  Data transfer between CPU and I/O module Data processing  Some arithmetic or logical operation on data Control  Alteration of sequence of operations  e.g. jump Amna Al-Ojeli Chapter 3 Combination of above William Stallings Computer Organization and Architecture 9th Edition Instruction Cycle State Diagram Amna Al-Ojeli Chapter 3 15  Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program  e.g. division by zero Timer  Generated by internal processor timer  Used in preemptive multitasking I/O  From I/O controller to signal completion of an operation or an error. Hardware failure Amna Al-Ojeli  e.g. memory parity error Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Interrupt Cycle Added to instruction cycle Processor checks for interrupt  Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending:  Suspend execution of current program  Save context  Set PC to start address of interrupt handler routine  Process interrupt Amna Al-Ojeli  Restore context and continue interrupted program Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 16  Connecting All the units must be connected Different type of connection for different type of unit  Memory  Input/ Output  CPU Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 1. Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals  Read  Write  Timing Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 17  2. Input/ Output Connection Similar to memory from computer’s viewpoint Output  Receive data from computer  Send data to peripheral Input  Receive data from peripheral  Send data to computer Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 2. Input/ Output Connection Cont. Receive control signals from computer Send control signals to peripherals  e.g. spin disk Receive addresses from computer  e.g. port number to identify peripheral Send interrupt signals (control) Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 18  3. CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Buses There are a number of possible interconnection systems Single and multiple BUS structures are most common  e.g. Control/Address/Data bus (PC) Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 19  What is a Bus? A communication pathway connecting two or more devices Usually broadcast Often grouped  A number of channels in one bus  e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Data Bus Carries data  Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 20  Address bus Identify the source or destination of data  e.g. CPU needs to read an instruction\ data from a given location in memory Bus width determines maximum memory capacity of system Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition Control Bus Control and timing information  Memory read/write signal  Interrupt request  Clock signals Amna Al-Ojeli Chapter 3 William Stallings Computer Organization and Architecture 9th Edition 21  UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 4 MEMORY SYSTEM Instructor: Amna Al-Ojeli Memory Hierarchy Registers  In CPU Internal or Main memory  May include one or more levels of cache  “RAM” External memory  Backing store Amna Al-Ojeli Chapter 4 William Stallings Computer Organization and Architecture 9th Edition 22 Amna Al-Ojeli Memory Hierarchy – Diagram Chapter 4 William Stallings Computer Organization and Architecture 9th Edition Performance Access time  Time between presenting the address and getting the valid data Memory Cycle time  Time may be required for the memory to “recover” before next access  Cycle time is access + recovery Transfer Rate Amna Al-Ojeli Chapter 4  Rate at which data can be moved William Stallings Computer Organization and Architecture 9th Edition 23  Access Methods Sequential  Start at the beginning and read through in order  Access time depends on location of data and previous location  e.g. tape Direct  Individual blocks have unique address  Access is by jumping to vicinity plus sequential search Amna Al-Ojeli  Access time depends on location and previous Chapter 4 location  e.g. disk William Stallings Computer Organization and Architecture 9th Edition Access Methods\ Cont. Random  Individual addresses identify locations exactly  Access time is independent of location or previous access  e.g. RAM Associative  Data is located by a comparison with contents of a portion of the store Amna Al-Ojeli  Access time is independent of location or previous Chapter 4 access  e.g. cache William Stallings Computer Organization and Architecture 9th Edition 24  Internal Memory Random Access Memory (RAM)  Misnamed as all semiconductor memory is random access  Read/Write  Volatile  Temporary storage  Static or dynamic Amna Al-Ojeli Chapter 4 William Stallings Computer Organization and Architecture 9th Edition Internal Memory Dynamic Random Access Memory (DRAM)  Bits stored as charge in capacitors\ Charges leak  Need refreshing even when powered  Simpler construction  Smaller per bit  Less expensive  Need refresh circuits  Slower  Main memory Amna Al-Ojeli  Essentially analogue Chapter 4  Level of charge determines value William Stallings Computer Organization and Architecture 9th Edition 25  Internal Memory Static Random Access Memory (SRAM)  Bits stored as on/off switches  No charges to leak  No refreshing needed when powered  More complex construction  Larger per bit  More expensive  Does not need refresh circuits  Faster Amna Al-Ojeli  Cache Chapter 4  Digital  Uses flip-flops William Stallings Computer Organization and Architecture 9th Edition Internal Memory Read Only Memory (ROM)  Permanent storage  Nonvolatile  Microprogramming  Library subroutines  Systems programs  Function tables Amna Al-Ojeli Chapter 4 William Stallings Computer Organization and Architecture 9th Edition 26  UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 5 CACHE MEMORY Instructor: Amna Al-Ojeli Location And Capacity ❖ Location  CPU  Internal  External ❖Capacity Word size - The natural unit of organization Number of words or Bytes Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 27  Unit of Transfer Internal  Usually governed by data bus width External  Usually a block which is much larger than a word Addressable unit  Smallest location which can be uniquely addressed  Word internally Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Cache Small amount of fast memory Sits between normal main memory and CPU May be located on CPU chip or module Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 28 Amna Al-Ojeli Cache/Main Memory Structure Chapter 5 Cache operation – overview CPU requests contents of memory location Check cache for this data If present, get from cache (fast) If not present, read required block from main memory to cache Then deliver from cache to CPU Cache includes tags to identify which block of Amna Al-Ojeli Chapter 5 main memory is in each cache slot William Stallings Computer Organization and Architecture 9th Edition 29 Amna Al-Ojeli Cache operation – Flowchart Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Cache Addressing Where does cache sit?  Between processor and virtual memory management unit  Between MMU and main memory Logical cache (virtual cache) stores data using virtual addresses  Processor accesses cache directly, not thorough physical cache  Cache access faster, before MMU address translation  Virtual addresses use same address space for different applications  Must flush cache on each context switch Amna Al-Ojeli Chapter 5 Physical cache stores data using main memory physical addresses William Stallings Computer Organization and Architecture 9th Edition 30  Mapping Function Fully Associative Mapping Set Associative Mapping Direct Mapping Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Fully Associative Mapping A main memory block can load into any line of cache Memory address is interpreted as tag and word Tag uniquely identifies block of memory Every line’s tag is examined for a match Cache searching gets expensive Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 31  Fully Associative Cache Organization Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Fully Associative Mapping\ Example Block size is 4 bytes  i.e. cache is 16k (214) lines of 4 bytes 16MBytes main memory 24 bit address  (224=16M) Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 32  Fully Associative Mapping\ Summary Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2s+ w/2w = 2s Number of lines in cache = undetermined Amna Al-Ojeli Chapter 5 Size of tag = s bits William Stallings Computer Organization and Architecture 9th Edition Set Associative Mapping Cache is divided into a number of sets Each set contains a number of lines A given block maps to any line in a given set  e.g. Block B can be in any line of set i e.g. 2 lines per set  2 way associative mapping  A given block can be in one of 2 lines in only one set Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 33  K- way Set Associative Cache Organization Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Set Associative Mapping\ Example Block size is 4 bytes  i.e. cache is 16k (214) lines of 4 bytes 16MBytes main memory 24 bit address  (224=16M) 13 bit set number Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 34  Set Associative Mapping\ Summary Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2d Number of lines in set = k Number of sets = v = 2d Number of lines in cache = kv = k * 2d Amna Al-Ojeli Chapter 5 Size of tag = (s – d) bits William Stallings Computer Organization and Architecture 9th Edition Direct Mapping Each block of main memory maps to only one cache line  i.e. if a block is in cache, it must be in one specific place Address is in two parts Least Significant w bits identify unique word Most Significant s bits specify one memory block The MSBs are split into a cache line field r and a Amna Al-Ojeli Chapter 5 tag of s-r (most significant) William Stallings Computer Organization and Architecture 9th Edition 35 Amna Al-Ojeli Direct Cache Organization Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Direct Mapping\ Example Block size is 4 bytes  i.e. cache is 16k (214) lines of 4 bytes 16MBytes main memory 24 bit address  (224=16M) Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 36  Direct Mapping\ Summary Address length = (s + w) bits Number of addressable units = 2s+w words or bytes Block size = line size = 2w words or bytes Number of blocks in main memory = 2s+ w/2w = 2s Number of lines in cache = m = 2r Size of tag = (s – r) bits Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Replacement Algorithms\ Direct Mapping No choice Each block only maps to one line Replace that line Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 37  Replacement Algorithms\ Associative & Set Associative Mapping Hardware implemented algorithm (speed) Least Recently used (LRU)  e.g. in 2 way set associative  Which of the 2 block is LRU? First in first out (FIFO)  Replace block that has been in cache longest Least frequently used (LFU)  Replace block which has had fewest hits Amna Al-Ojeli Chapter 5 Random William Stallings Computer Organization and Architecture 9th Edition Write Policy Must not overwrite a cache block unless main memory is up to date Multiple CPUs may have individual caches I/O may address main memory directly Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 38  Write Policy\ Write Through All writes go to main memory as well as cache Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date Lots of traffic Slows down writes Remember bogus write through caches! Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition Write Policy\ Write Back Updates initially made in cache only Update bit for cache slot is set when update occurs If block is to be replaced, write to main memory only if update bit is set Other caches get out of sync I/O must access main memory through cache N.B. 15% of memory references are writes Amna Al-Ojeli Chapter 5 William Stallings Computer Organization and Architecture 9th Edition 39  Unified VS. Split Caches One cache for data and instructions or two, one for data and one for instructions Advantages of unified cache  Higher hit rate ▪ Balances load of instruction and data fetch ▪ Only one cache to design & implement Advantages of split cache  Eliminates cache contention between instruction fetch/decode unit and execution unit Amna Al-Ojeli Chapter 5 ▪ Important in pipelining William Stallings Computer Organization and Architecture 9th Edition UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 6 VIRTUAL MEMORY Instructor: Amna Al-Ojeli 40  Virtual Memory It is a technique for using the secondary storge (hard disk) to extend the apparent limited site of the physical memory (main memory). If the segment of the program containing the word requested by the processor is not in the main memory at the time of the request, then such segment will have to be thought from the disk to Amna Al-Ojeli the main memory. Chapter 6 William Stallings Computer Organization and Architecture 9th Edition Virtual Address The address issued by the processor in order to access a given word does not correspond to the physical memory space is called a virtual (logical) address. Memory Management Unit (MMU) is responsible for the translation of virtual addresses to their corresponding physical addresses. Amna Al-Ojeli Chapter 6 William Stallings Computer Organization and Architecture 9th Edition 41  Page Movement of data between the disk and the main memory takes the form of pages. Page is a collection of memory words, which can be moved from the disk to the main memory when the processor requests accessing a word on that page. Amna Al-Ojeli Chapter 6 William Stallings Computer Organization and Architecture 9th Edition Page Page fault  Required page is not in memory  Operating System must swap in required page  May need to swap out a page to make space  Select page to throw out based on recent history Demand paging  Do not require all pages of a process in memory  Bring in pages as required Amna Al-Ojeli Chapter 6 William Stallings Computer Organization and Architecture 9th Edition 42  Page Table It is a table which contains the mapping of virtual pages to physical frames and it is stored in the main memory. The page table contains:  Modification of a page  The authority for accessing a page  A bit indicating the validity of a page (The valid bit)  The other control bit that is kept in the page table is Amna Al-Ojeli the dirty bit Chapter 6 William Stallings Computer Organization and Architecture 9th Edition Translation Lookaside Buffer In the most modern computer systems a copy of a small portion of the page table is kept on the processor chip. This portion consist of the page table entries that correspond to the most recently accessed pages. This small portion kept in the Translation Lookaside Buffer. TLB works in the same way as an ordinary memory Amna Al-Ojeli Chapter 6 cache. William Stallings Computer Organization and Architecture 9th Edition 43  TLB Operation Amna Al-Ojeli Chapter 6 UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 7 INPUT/ OUTPUT Instructor: Amna Al-Ojeli 44  Input/Output Problems In addition to the processor and a set of memory modules, the third key element of a computer system is a set of I/O modules. Wide variety of peripherals  Delivering different amounts of data  At different speeds  In different formats All slower than CPU and RAM So, there is needed to I/O modules Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition Input/Output Module The I\O module has two major functions:  Interface to the processor and memory via the system bus or central switch  Interface to one or more peripheral devices by tailored data links Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition 45  External Devices External devices classified into three categories: ❖Human readable: suitable for communicating with the computer user  Screen, printer, keyboard ❖Machine readable: suitable for communicating with equipment  Monitoring and control ❖Communication: suitable for communicating with remote devices Amna Al-Ojeli  Modem Chapter 7  Network Interface Card (NIC) William Stallings Computer Organization and Architecture 9th Edition I/O Module Function 1. Control & Timing 2. CPU Communication 3. Device Communication 4. Data Buffering 5. Error Detection Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition 46  I/O Steps 1. CPU checks I/O module device status 2. I/O module returns status 3. If ready, CPU requests data transfer 4. I/O module gets data from device 5. I/O module transfers data to CPU Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA) Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition 47  Programmed I/O CPU has direct control over I/O  Sensing status  Read/write commands  Transferring data CPU waits for I/O module to complete operation Wastes CPU time Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition Interrupt Driven I/O Overcomes CPU waiting No repeated CPU checking of device I/O module interrupts when ready Amna Al-Ojeli Chapter 7 William Stallings Computer Organization and Architecture 9th Edition 48  Direct Memory Access Interrupt driven and programmed I/O require active CPU intervention  Transfer rate is limited  CPU is tied up DMA is the answer Efficient technique used when large volumes of data are to be moved  Additional Module (hardware) on bus Amna Al-Ojeli Chapter 7  DMA controller takes over from CPU for I/O William Stallings Computer Organization and Architecture 9th Edition UNIVERSITY OF BENGHAZI FACULTY OF INFORMATION TECHNOLOGY COMPUTER ARCHITECTURE Chapter 8 Processor Structure and Function Instructor: Amna Al-Ojeli 49  CPU Structure CPU must:  Fetch instructions  Interpret instructions  Fetch data  Process data  Write data Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition Data Flow (Instruction Fetch) Depends on CPU design In general: Fetch  PC contains address of next instruction  Address moved to MAR  Address placed on address bus  Control unit requests memory read  Result placed on data bus, copied to MBR, then to IR Amna Al-Ojeli Chapter 8  Meanwhile PC incremented by 1 William Stallings Computer Organization and Architecture 9th Edition 50  Data Flow (Data Fetch) IR is examined If indirect addressing, indirect cycle is performed  Right most N bits of MBR transferred to MAR  Control unit requests memory read  Result (address of operand) moved to MBR Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition Data Flow (Fetch Diagram) Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition 51  Data Flow (Execute) May take many forms Depends on instruction being executed May include  Memory read/write  Input/Output  Register transfers  ALU operations Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition Data Flow (Interrupt) Simple Predictable Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Amna Al-Ojeli Chapter 8 Next instruction (first of interrupt handler) can be fetched William Stallings Computer Organization and Architecture 9th Edition 52  Prefetch Fetch accessing main memory Execution usually does not access main memory Can fetch next instruction during execution of current instruction Called instruction prefetch Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition Improved Performance But not doubled: Fetch usually shorter than execution  Prefetch more than one instruction? Any jump or branch means that prefetched instructions are not the required instructions Add more stages to improve performance Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition 53  Pipelining Fetch instruction Decode instruction Calculate operands Fetch operands Execute instructions Write result Amna Al-Ojeli Chapter 8 Overlap these operations William Stallings Computer Organization and Architecture 9th Edition Timing Diagram for Instruction Pipeline Operation Amna Al-Ojeli Chapter 8 54  Six-Stage CPU Instruction Pipeline Amna Al-Ojeli Chapter 8 Pipeline Hazards Pipeline, or some portion of pipeline, must stall Also called pipeline bubble Types of hazards  Resource  Data  Control Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition 55  Resource Hazards Two (or more) instructions in pipeline need same resource Executed in serial rather than parallel for part of pipeline  Also called structural hazard E.g. Assume simplified five-stage pipeline and each stage takes one clock cycle Ideal case is new instruction enters pipeline each clock cycle  Assume main memory has single port Assume instruction fetches and data reads and writes performed one at a time, ignore the cache Operand read or write cannot be performed in parallel with instruction fetch Fetch instruction stage must idle for one cycle fetching Amna Al-Ojeli I3 Chapter 8 Solution: increase available resources. E.g. multiple main memory ports William Stallings Computer Organization and Architecture 9th Edition Resource Hazard Diagram Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition 56  Data Hazards Conflict in access of an operand location Two instructions to be executed in sequence Both access a particular memory or register operand If in strict sequence, no problem occurs If in a pipeline, operand value could be updated so as to produce different result from strict sequential execution Pipeline must stall for clocks cycles Amna Al-Ojeli Without special hardware and specific avoidance Chapter 8 algorithms, results in inefficient pipeline usage William Stallings Computer Organization and Architecture 9th Edition Data Hazard Diagram Amna Al-Ojeli Chapter 8 William Stallings Computer Organization and Architecture 9th Edition 57  Control Hazards Also known as branch hazard Pipeline makes wrong decision on branch prediction Brings instructions into pipeline that must subsequently be discarded Dealing with Branches  Multiple Streams  Prefetch Branch Target  Loop buffer  Branch prediction Amna Al-Ojeli Chapter 8  Delayed branching William Stallings Computer Organization and Architecture 9th Edition Acronyms MAR Memory Address Register MBR Memory Buffer Register IR Instruction Register IAR Instruction Address Register MMU Memory Management Unit PC Program Counter LRU Least Recently Used LFU Least Frequently Used FIFO First In First Out I\O Input/Output OS Operating System Amna Al-Ojeli Acronyms William Stallings Computer Organization and Architecture 9th Edition 58  Acronyms IAS Institute for Advanced Studies CPU Central Processing Unit ALU Arithmetic Logic Unit CU Control Unit RAM Random-Access Memory ROM Read-Only Memory DRAM Dynamic Random-Access Memory DMA Direct Memory Access Amna Al-Ojeli Acronyms William Stallings Computer Organization and Architecture 9th Edition 59