آلية الإنتقالات في الحاسوب

Computer Architecture

• Computer architecture encompasses the attributes of a computer that are visible to the programmer. These include the instruction set, data representation, I/O mechanisms and addressing techniques.
• Computer organization describes how features are implemented. Components like control signals, interfaces, and memory technology are vital for understanding how the computer actually works. The organization clarifies the structure.

Structure and Function

• Structure in computer architecture describes the arrangement of its components and their relationship to one another.

• Function describes the operation of each individual component within the overall structure.

Operations

• Data movement: The computer enables data transfer between itself and the external world.

• Storage: The computer temporarily stores data being processed.

• Processing: Data is processed, manipulated, and transformed.

• Processing from storage to I/O: Data is processed or prepared to be available to external devices.

The Computer- Top Level Structure

• The diagram illustrates the interconnect between the CPU, main memory and I/O.

The Processor

• The processor's primary function is fetching and executing instructions.

• Key components include the Arithmetic Logic Unit (ALU) for calculations, a Control Unit for issuing control signals, and various registers (PC, MAR, MDR, ACC) for temporary storage.

Von Neumann Machines

• This architecture is a widely used model for modern computers where both instructions and data are stored in a common memory.

• The machine uses the stored-program concept where data and instructions are stored in the same memory area.

Von Neumann Machines (continued)

• Main memory stores programs and data.

• Arithmetic and Logic Unit (ALU) performs operations on binary data.

• Control Unit manages and executes instructions.

• Input/Output (I/O) mechanisms are managed by the control unit.

• The IAS computer exemplified this architecture, developed at the Princeton Institute for Advanced Studies.

Computer Registers

• Registers are storage locations within the CPU.

• The Memory Buffer Register (MBR) holds data to be written or read from memory/I/O.

• The Memory Address Register (MAR) specifies the address in memory.

• The Instruction Register (IR) contains the current instruction being executed.

• Other registers include the Instruction Buffer Register & Program Counter.

IBM Systems

• IBM was a leading manufacturer, producing stored-program computers (like the 701 and 702) that were used for scientific calculations and business applications.

Transistors

• Transistors replaced vacuum tubes, leading to smaller and more efficient systems.

Semiconductor Memory

• Semiconductor memory, appearing in the 1970s, significantly increased memory capacity and speed over magnetic core technology.

Evolution of Intel Microprocessors

• Initially for specific applications processors like the 4004 were developed.

• Subsequent models such as the 8008 showed increasing complexity and capacity.

Speeding It Up

• Techniques like branch prediction, data flow analysis, and speculative execution aim to make instruction execution more efficient.

What is a program?

• A program is a sequence of steps, each requiring unique control signals for arithmetic or logical operations.

Function of Control Unit

• The Control Unit receives a code for each operation.
• It then issues control signals.

Components

• The Control Unit and Arithmetic Logic Unit (ALU) together form the Central Processing Unit.

• Input/Output (I/O), and main memory work with the CPU.

Instruction Cycle

• The instruction cycle consists of fetch and execute cycles.

• Fetch Cycle: The processor gets the next instruction from memory, then increments the PC.

• Execute Cycle: The processor interprets and performs the instruction. This may involve processor-memory operations or data processing.

Execute Cycle

• Processor-memory: Copying data between the processor and memory.

• Processor-I/O: Transferring data between the processor and an I/O module.

• Data processing: Performing arithmetic or logical operations on data.

• Control: Changing sequence of operations (e.g. jumps).

Interrupts

• An interrupt is a mechanism that allows other modules (like I/O) to interrupt normal processing.

• Several sources include program errors, timers, and external devices needing service.

• The interrupt cycle checks for interrupt signals and then handles them (e.g., saving the current program context, performing the requested action, and then restarting).

Connecting

• Connecting different units involves a tailored approach depending on the devices involved.
• Different connection types serve different devices.

Memory Connection

• Memory receives and sends data.
• It takes addresses (locations), and control signals (Read/Write).
• Timing is crucial for the memory connections.

Input/Output (I/O) Connection

• The I/O module receives data from the CPU, and sends it to devices or peripherals.
• Performs translations, and manages control signals.

CPU Connection

• The CPU reads instructions and data.
• Writes data & controls other units.

Buses

• Interconnections in computers frequently use buses; these may have a single or multiple channels for control, addressing, and data.

What is a Bus?

• A bus is a communication pathway connecting multiple devices.

• Buses are frequently grouped into channels for control and data transfer.

Address Bus

• The address bus identifies the source or destination of data.

• The width of the bus impacts the maximum memory capacity.

Control Bus

• The control bus conveys control and timing signals.

• Signals for read/write operations, interrupt requests, and clocks are conveyed through the control bus.

Memory Hierarchy

• Registers: Stored within the CPU.

• Internal/Main memory: Stored internally by using caches.

• External memory: Includes backing stores and external devices.

Memory Hierarchy - Diagram

• A visual representation of the various levels in the memory hierarchy.

• Levels range from faster, smaller registers to slower, larger external memory.

Performance

• Access time: Time interval between the address request and receiving valid data.

• Memory cycle time: The time taken by memory to recover from an access operation.

• Transfer Rate: Rate at which data can be transferred from the memory to the connected unit.

Access Methods

• Sequential: Data are accessed in sequence, starting from the beginning.

• Direct: Data access is based on a specific address/location plus a sequential search.

• Random: Access time is independent of the location of the data.

• Associative: Access time is independent of the location, it depends on matching data.

Internal Memory

• Random Access Memory (RAM): Volatile memory where data can be read and written to.

• Static Random Access Memory (SRAM): Bits are represented as switches, reducing the need for refreshing.

• Dynamic Random Access Memory (DRAM): Uses capacitors to store bits and requires constant refreshing.

• Read-Only Memory (ROM): Non-volatile memory for permanent storage (library subroutines, systems programs, functions).

Location and Capacity

• Location: Internal or external to the CPU.

• Capacity: Characterized by word size (the fundamental unit in the system), and the number of words or bytes that can be stored.

Unit of Transfer

• Internal: Usually governed by data bus width.

• External: Typically a block larger than a word, allowing larger data transfers.

Cache

• A smaller, faster memory between main memory and CPU.

• It stores frequently accessed data.

Cache/Main Memory Structure

• Shows the relationship between cache and main memory.
• Data is fetched and stored in blocks.

Cache Operation – Overview

• CPU requests data from memory.

• The cache quickly checks for the needed data.

• If present (a cache hit), data is delivered quickly.

• If not present (a cache miss), data is retrieved from main memory, and then moved to the cache.

Cache Addressing

• Addresses are translated based on the addressing scheme for cache.

• Virtual and physical addresses are handled to access data.

Mapping Function

• Fully Associative: Allows any memory block to be placed in any cache line.
• Set Associative: Arranges cache into sets; a specific block can exist in any valid line within a given set.
• Direct Mapping: Each block from main memory maps to only one specific cache line.

Fully Associative Mapping

• A main memory block can be loaded into any cache line
• Interpreted as tag and word

Set Associative Mapping

• The cache is divided into sets.
• A block can be in one of several lines, in a given set.

Direct Mapping

• Each main memory block maps to a specific cache line.
• Least significant bits are part of the word; the most significant specify the memory block.

Replacement Algorithms/ Direct Mapping

• A replacement algorithm in cases of cache misses decides which memory block will be overwritten in the cache.

• No choices are available; the processor simply replaces the specific line.

Replacement Algorithms/ Associative & Set Associative Mapping

• Several algorithms exist for choosing which cached data to evict (replace). These often prioritize recently used blocks to improve cache efficiency.

Write Policy

• Write Through: All writes are done to both the cache and main memory.

• Write Back: Updates are in cache only; main memory is updated when the block is replaced.

Unified vs. Split Caches

• Unified caches use a single cache for both instructions and data.

• Split caches use separate caches for instructions and data, often resulting in better performance by reducing conflicts.

Virtual Memory

• Virtual Memory uses secondary storage (like hard disk) as an extension of the main memory.

• The system translates virtual addresses to their corresponding physical addresses.

Page

• Movement between disk and main memory happens in units called pages.

• These pages can be loaded to main memory when needed.

Page Fault

• Page Fault occurs when the requested page is not in main memory.

• Operating System must swap in or locate a suitable existing page to replace for the required page.

Page Table

• A page table stores the mapping between virtual pages and physical frames in main memory.

Translation Lookaside Buffer (TLB)

• TLB is a cache that stores frequently used translations of virtual addresses to physical addresses. It speeds up virtual memory accesses.

I/O Problems

• I/O modules handle connections to various peripherals.

• Dealing with varied speeds and data formats requires efficient management.

External Devices

• External devices are classified into:
  • Human-readable (e.g., monitor, keyboard)
  • Machine-readable (e.g., printers, scanners)
  • Communication devices (e.g., modems, network interfaces).

I/O Module Function

• Control and timing: Controlling and synchronizing I/O operations.

• CPU communication: Providing an interface for the CPU and peripherals to communicate.

• Device communication: Communication with various I/O device types.

• Data buffering: Storing data temporarily during transfer between I/O modules and CPU.

• Error detection: Detecting errors during I/O operations.

I/O Steps

• Check device status.

• Return status results.

• If ready, the CPU can request data transfer.

• I/O module gathers data from devices.

• Transferring data to the CPU.

Input/Output Techniques

• Programmed I/O: CPU directly controls the I/O actions.
• Interrupt-driven I/O: Devices interrupt the CPU when ready.
• Direct Memory Access (DMA): DMA controller handles data transfer between memory and I/O modules without involving CPU.

CPU Structure

• The CPU fetches, decodes, and executes instructions.

• Instructions are fetched from memory and decoded internally to be executed by circuits in the CPU.

• Data is fetched from memory, processed or manipulated in the Arithmetic Logic Unit, then may be stored in memory.

Data Flow (Instruction Fetch)

• The CPU examines the Program Counter (PC) for the address of the next instruction and then fetches the instruction.

Data Flow (Data Fetch)

• If indirect addressing, then the CPU fetches the actual address of the operand from memory.
• For both instruction fetch and data fetch, the CPU requests the Memory.
• Result is kept in Memory Buffer Register.

Data Flow (Execute)

• Instructions are carried out, data and operands are retrieved for execution, and results are then saved.
• The execute portion depends on the instruction that is being fetched.

Data Flow (Interrupt)

• Interrupts suspends the current process to respond to higher priority tasks.

• Interrupt handling routines are used to manage I/O requests or errors.

Prefetch

• The CPU looks ahead in the instruction stream and fetches the next instruction while the current one is being executed.

Improved Performance

• Prefetching attempts to speed up execution by performing some operations in advance.
• However, jumping or branching can cause wasted prefetches.

Pipelining

• The instruction processing is divided into overlapping stages, improving efficiency.

Pipeline Hazards

• Resource hazards: Conflicts when multiple instructions require the same resource (hardware or memory).
• Data hazards: Conflict when instructions in a pipeline depend on the previous one; the data needed for calculation is not available immediately.
• Control hazards: Conflicts happen in cases of branches or jumps.

اختبر معلوماتك حول آلية الإنتقالات في الحاسوب من خلال هذا الاختبار. يتناول الأسئلة كيفية عمل الإشارات المختلفة وأهمية الاتصال بين وحدات الحاسوب. ستساعدك هذه المعلومات على فهم كيفية إدارة عمليات الإدخال والإخراج.