Silicon Earth: Chapter 7 PDF

208 Silicon Earth: Introduction to Microelectronics and N deposited on both horizontal and vertical surfaces at similar rates, and can thus steps in the crystal surface and fill cavities in the surface, often...

208 Silicon Earth: Introduction to Microelectronics and N deposited on both horizontal and vertical surfaces at similar rates, and can thus steps in the crystal surface and fill cavities in the surface, often Nanote indispensable both chnol zy coNer If we wanted to deposit polysilicon (poly) on the wafer, we can also do that by using silane, according to with attribLPCVD utes. SiH, ’ Si + 2H,. We might even choose to dope the polysilicon as we deposit it [e.g., (710) phine (PH,)nasty stuff that supposedly smells like almonds, but so n-type using phos- wickedly have to wonder how anyone actually knows what it smells like and lived to toxic you tell!]. kAlas, silane is extremely explosive (and toxic). If you happen to ever visit a real fabrication ity you will note that the 50 ft tall, large white silane cylinders are conveniently removed few hundred feet from the main building and placed in what are affectionately krna a "bunkers"-you get the idea! Exceptionally sensitive gas detectors and all sorts ofss measures for things like silane and phosphine handling are a dime-a-dozen in the fab obvious reasons (okay, $100,000 a dozen!). Polysilicon is very commonly used in fab tion when we do not need a perfect silicon crystal, but still requirea doped silicon laver to serve as agood conductor, and it can be put downdirectly on oxide, forinstance, to isoaie it electrically from the silicon crystal. Finally, an alternative dielectric to oxide is silicon nitride ("nitride" for short), which we can deposit with LPCVD by using silane plus ammonia: 3SiH, + 4NH, ’ Si,N, + 12H,. (711) Nitride is not as good an insulator as oxide, but importantly it has very diferent etching (next topic) properties and thus is often essential in the fabrication process. Etching and Polishing Awesome! Crystal-construction platform? Check. Means to dope said crystal? Check Way to sequentially grow and deposit new materials on said crystal? Check. Now need a way to selectively remove those materials ("etch" them), either fromwillthesee,crysa etch- layer itself or from the various layers we just took pains to deposit. As we the transis- ing will prove indispensable for selectively patterning layers as we build up tor from scratch. bathof some There are two basic ways to etch deposited materials:"wet etching," using a liquid etchant to eat away the material in question (this is intuitive), and "dry ercs perhaps less using a reactive "plasma" to whisk away the material in question (this is 735), butmaterial is con- intuitive). Abasic chemical-etching systemis not much to look at (Figure for the ceptually very simple in its operation:(1) Create a vat of very pure etchant letthe into said vat, (3) Finito. Of in question, (2) lower your wafer containingthe deposited material it off. etchant eat away said material for time t, (4) remove wafer, and then rinse might art(it mnm course, controlling the precise amount of material that is etched can be a fine across a 300 only be afew microns, or even 10s of nanometers), and doing it uniformly processisfairly wafer with 500,000,000 features to be etched is an even finer art. Still, the routine today. Bricks and Mortar: Micro/Nanoelectronics Fabrication 209 FIGURE 7.35 An automated wet-etching tool. (Courtesy of Intel Corporation, Santa Clara, CA.) Asan example, a very common etchant for oxide is buffered hydrofluoric acid (BHF). I wouldn't advise dipping your fingers into it! BHF is an especially nice etchant because it attacks oxide but does not attack silicon. Hence, if I lower my wafer with oxide deposited on top into a vat of BHE, the oxide wiil etch until it reaches the silicon and then stop, no matter how long it stays in thebath (amazingly, called an "etch stop"). In thiscase, BHF is said to have good etch selectivity" tosilicon (doesn't etch it). If Ifurther pattern apro tective layer on top of the oxide in a particular shape (this is called an 'etch mask") that does not etch in BHF (an organic photoresist would be a good example of an etch mask on oxide-see the "Photolithography" section), then Ican use BHF to "transfer" that pat terned shape onto the surface of the wafer (meaning: BHF etches the oxide down to the silicon everywhere except where I put the protective etch mask--instant pattern transfer). If Iinstead wanted to etch silicon (or polysilicon), for instance, I might use potassium hydroxide (KOH).KOH has good selectivity to both oxide and nitride, with silicon "etch rates' of approximately 2um/min. An oxide layer underneath a polysilicon layer could be used as an etch stop in this case. Interestingly, KOH also attacks different silicon crystaldirections at different etch rates. For example, the differential etching ratio for : directions (don't panic--simply two different directions in the crystal lat tice,one at a45° angleto the other)can be as high as 400:1; meaning, if Iopenapattern in an oxide etch stop on the surface of a silicon wafer and simply expose the wafer to KOH, Ican trivially etch deep V-shaped groves into the silicon surface. If I instead use a wider rectangular-shaped pattern, Ican actually control the etch depth independent of the etch time, creating a self-limiting deep etch (quite clever and useful). As we will see in a later chapter, such etching techniques form the basis of so-called "bulk micromachining" used in MEMS/NEMS technology. So why wet versus dryetching? Well, it relates to the resultant "etch profile" desired. As illustrated in Figure 7.36, wet etching typically has an "isotropic" etch profile (etches the same in alldirections), whereas dry etching can be easily tailored to create a number of useful "etch profiles," from isotropic to"anisotropic" (etches in only one direction) to etch narrowbut deep "trenches" into the various materials. Anisotropic etching becomes espe cially importanit as the shapes to be etched get finer and finer and more closely packed, because wet etching tends to undercut the etch mask, "blowing up" or "ballooning out"  Silicon Earth:Introduction to. Microelectronics and Nanotechnol rgy 210 Etch profile Type of etch Sidewall profile Visual Wet etch Isotropic Dry etch Isotropic Anisotropic Anisotropic (tapered) Silicon trench FIGURE 7.36 dry-etching processes. The sidewall etch profiles for both wet- and limiting be etched carn be placed how close two shapes totransistor shapes during etching, hence and hence hoW fundamentally determines the size of the to one another. This (read: a big deal). many transistors per IC there can be yeah?!Think back to high schol Dry etching isperformed with a reactive "plasma."Oh Aplasa Plasmafourth state of matter (solid, liquid, gas,plasma). eleectrical), chemistry. Got it? Yep! (typically applied to it in some form is essentially a gas that has had energy the gas molecules. and thus creating an 10grander electrons from a stripping the valence action? Well, think fluorescent light; ot, on oneof gas (literally a gas of ions). Plasma in sidebar). In our case, Aurora Borealis" the resul- scale, the aurora borealis (see the "Geek Trivia: gas toionize, starting the nice features of plasmas is that if we choose the right great etchant. tant plasma can be very chemically reactiveread: a polarnight GEEK TRIVIA: AURORA BOREALIS in seen namedfor lights sometimes The aurora borealis is the origin of the haunting glowing as the aurora borealis, north wind. skies. At northern latitudes, this phenomenon is knownthe Greek name for the norther Boreas, onlyin regions Aurora, the Roman goddess of the dawn, and because it is visible polar eithe The aurora borealis is often calledthe "northern lights" southern Aurorasof March to April. Inthe Latin. Come from skies, typically from September to October and South" in that magnetic we instead have the aurora australis; australis meaning "ot the (e.g., electrons) Earth's atitudes type are caused by the collision of energetic charged particles trapped inthe at dominatedbr the solar wind or coronal storms and then are subsequently atmosphere(often wae nm field (magnetosphere), with gas atoms found inthe Earth's upper aurorais often558 an (at above 80 km), creating glowing plasmas. Light emittedghostly during greenish glowFigure11.10. emission from an oxygen plasma, resulting in either a cool pics see length) or a sunrise-like dark-red glow(at 630 nm). For Some Bricks and Mortar: Micro/Nanoelectronics Fabrication 211 Process gases Process chamber Plasma Magnet coils Chuck Si wafer Exhaust gases RF power Backside cooling helium FIGURE 7.37 Illustration of a plasma-etching system. (Inspired by Anderson, B.L. and Anderson, R.L., Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 2005.) In atypical plasma-etching system (Figure 7.37), an appropriate etch gas is introduced into the chamber, and is then ionized by use of RF power (high-frequency EM energy) at 13.56 MHz (no real magic on the number; it is set by the FCC). The energetic plasma ions then bombard the surface, suitablyprotected by an etch mask in various regions we do not want to etch. The ions bond with the target host atoms to be etched and are whisked away and sucked out of the chamber as exhaust (Figure 7.38). Because we can also apply a DCelectric field to the plasma that the ions will respond to, we have easy directional etch control in the plasma process, allowing us to produce sharp anisotropic etch profiles. Such aplasma-etching system is often called a "reactive ion etching" tool, or RIE for short (Figure 7.39). Typical RIE etch gases include SF, arnd O, for organic films, Etching Etchant ions Photoresist PR PR Incident Exposed ions atom Broken bonds FIGURE 7.38 Illustration of the plasma-etching process. 212 Silicon Earth: Introduction to Microelectronics and Nanotechnol gy FIGURE 7.39 A reactive ion etcher in action. (Courtesy of Texas Instruments, Inc., Dallas, TX.) CCI, and CF,for polysilicon,C,F, and CHE, for oxides, etc. More sophisticated RIE tools used today for etching very deep (100s of microns), high-aspect-ratio (deep but narrow) trenches include inductively-coupled-plasma (ICP) tools, a workhorse in the MEMS/ NEMS field. The final commonly used material removal technique in microelectronics is called CMP, and represents an interesting combination of both chemical etching and mechani cal abrasion. Although a relative latecomer to the fab bag of tricks (1990s), CMP is now ubiquitousin modern IC manufacturing, particularly in back-end-of-the-line (BEOL P narization (to make flat). The need is obvious. As we build up the many levels of me could be 8-14 dielectric/metal/dielectric needed for interconnecting modern ICs (thissurface for that levels), we continue to deposit many additional new layers. If the starting metal wires that BEOL process is not perfectly flat, it strongly affects the density of theflatten (planarize) can be placed on any given layer. The question is one of how best to Neither wet the surface of an entire 300 mm wafer without harming what is underneath. CMP!In here. Answer: upside etching nor dry etching will do the planarization trick needed isturned CMP, a chemical "slurry'" is used as an etchant or abrasive, and the waferagainst theCMP down, slowly rotated, with backside pressure pushing the wafer down grinding lens and "pad" to effectively grind away the surface topography(much like opticalnm/min rangepres- the 100 pH, applied and polishing). Material removal rates are generally slow, in chemical endoe can be controlled precisely by varying the slurry flow and business the manutacturing wafer polish sure, rotational speed, and temperature. CMP is also used to processing silicon wafers to achieve the atomic flatness needed for beginning Semiconductor shownin It still surprises me that CMP, arguably the most brute-force system islayersot technique, works so well; but alas, it does! Aschematic of a CMPinterconnect clearly can Figure 740, and if you refer to Figure 7.45, which showsthe BEOL you CMIPSo a complementary metal oxide semiconductor (CMOS) microprocesso, tof footprint see the beautifully planarized metal/dielectric layers, the singular much for etching and polishing. Now on to shape patterning. Bricksand Mortar: Micro/Nanoelectronics Fabrication 213 Pressure applied Si wafer 0Abrasive slurry Pad Wafer topography Platen FIGURE 7.40 Illustration of a CMP system. (Inspired by Pierret, R.E, Semiconductor Fundamentals, Addison-Wesley, Reading, MA, 1996.) Photolithography The essential step in all of microelectronics fabrication is the pattern transfer process previ ously alluded to. That is, how do we go from a rectangular shape of dimension x x y on my computer screen where I am designing Mr. (Ms.?) Transistor to implementing that identi cal shape in material z on the surface of my silicon wafer? That pattern transfer process is called "photolithography" or simply "lith" to those in-the-know. Amodern IC might require upward of 40 distinct lith steps, and given the scale of lith involved in building say a microprocessor, which might require patterning 500,000,000 rectangles that are 32 nm on a side on a single ICin a single lith step, clearly lith is the most delicate and hence costly processing step used in semiconductor manufacturing (by far). In fact, we classify the fab facility by its lith capabilities: Building Ais a 32 nm fab, Building Bis a 180 nm fab, etc. So what's the deal with lith? In short, to fabricate an IC, thin films (think fractions of a micron thick) of various materials must be deposited onto the wafer toact as etch stops, ion implantation ordiffusion barriers, conductors, insulators between conductors, etc. Those thin films typically need to be patterned into particular shapes on the wafer, or holes ("windows) must be etched intothe films toeither allow dopants through or to make an electrical contact between twodifferent layers. These wafer patterns are first designed on acomputer,and then are transferred to a photolithographic "mask" and subsequently onto the surface of the wafer. Lith uses an exceptionally elegant photo-engraving process much likethat used in conventional film photography. (Hopefully at least a few of you still own a non-digitalcamera? Right, Iknow, wishful thinking!) The mask patterns are first trans ferred from the mask onto a light-sensitive organic material called a photoresist ("resist"), and then either dry or wet etching is used to transfer the final pattern from the resist to the thin film in question.  SiliconEarth: Introduction to Microelectronics and N Nanotechnol gy 214 is itself made up of a Each lith step (pattern transfer sequence) 741. Let's imagine thatnumber of ual processing steps, as illustrated in Figure I have a on the transistor. Here's how I would individ. I want to create in a polysilicon layer go about this: tectangle use lith to Deposit the poly by using LPCVD across the entire wafer. This would be called a "blanket film deposition." Apply a chemical primer (think paint) or adhesion layer to the blanket poly film to help the resist stick to the thin film. Typically hexamethyldisilazane (HMDS obvious reasons) is used. Spin on the resist (literally rotate the wafer at high (1000-5000) rpm'ss and drop on the liquid resist so that it "spin-coats" the whole water to a given well-controlod thickness of a fraction of a micron to several microns, depending on the lith stenl Cook the resist at low temperature (maybe 80°C-this is calleda "soft-bake") Apply the mask by using a lith exposure system. Align the mask to the wafer (this obviously gets tricky if Ihave to align this mask resolution). to apreviously patterned layer, to a fraction of amicron Expose the wafer to light (actually a laser). Wherever the shape is not present on the mask will be exposed to the light, chemically altering its polymer structure. Remove the mask. Soft-bake the wafer again to solidify the chemical changes to the resist. "Develop" the resist (think old-school photography), using a wet etch to dissolve allof the resist exposed to the UV light (burning off the resist with plasma etching in oxygen"resist ashing"-is also used). Cook it once more at a higher temperature ("hard-bake") of maybe 150°C to toughen the resist to plasma etching. smoothly ("lith Get it under the microscope and make sure everything went inspection"). Revwork if needed; else, the lith step is done. the resist?! Yup. Whew! Twelve separate steps just to get the image from the mask ontoexposethe wafer With the intended pattern now safely transferred into the resist, we can andthenuse to a plasma etch to remove the poly everywhere but under the resist pattern, peekunderthe a different wet etch (or plasma) to remove the final resist. Now take a finalcompletely trans microscope to ensure all is well. Look okay? Good. Theimage is now photo-engraving ferred from the mask into the poly. Clever, huh?! Basically, lith is just a process, but on ahighly miniaturized scale. myrct I design A word or two more about the masks used to expose the resist. First,(remember-there single angles for my IC on the computer, where I can easily manipulate them layer tora data could be 500,000,000 of these submicron-sized objects for a given mnask aselectronic op" IC, and maybe 40 different layers needed!). Next, I feed those rectangles essentiallyathan reticle is larger to a "pattern generator" that replicates them on a"reticle." The 5x 10x "step-and-repeat or of what was on my computer screen, except that it is generally made and over the original drawn images (i.e., it is a magnified version of the design). A lith mask inchuded camera (well named) is then used to replicate the reticle on a masterfinalIC) are over again, suchthat manyidentical copies of the reticle (one for each Bricks and Mortar: Micro/Nanoelectronics Fabrication 215 Gate oxide Polysilicon Oxide Si wafer Polysilicon p-Well (a) Starting wafer Photoresist Polysilicon Oxide Si wafer p-Well (b) Photoresist applied Gate mask Photoresist Polysilicon Oxide Photoresist Si wafer Polysilicon STI p-Well (c) Mask applied Polysilicon Oxide Siwafer Polysilicon STI p-Well Pattern developed FIGURE 7.41 of lllustration of the photolithography process. (Inspired by Anderson, B.L. and Anderson, R.L, Fundamentals Semiconductor Devices, McGraw-Hil, New York, 2005)  Silicon Earth: Introduction to) Microelectronics and Nanotechnol gy 216 Light source Reticle Projection lens Si wafer FIGURE7.42 and Anderson, R.L., Representation of an optical projection lithography system. (Inspired by Anderson, B.L. Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 2005.) x mm on the mask. For instance, on a 200 mm mask, wwe can place 1200 copies of a 5 mm which a tin IC (5). The final lith mask is essentially a piece of high-quality glass ontoa pristine mas metal coating (typically chrome) has been applied, which can now serve as ter photographic plate for use in lith (the chrome patterns are also defined through the use of a lith process). One such mask is needed for each lith step, A complete set of state" of-the-art masks (again, there might be 40) might cost $1,000,000 and are easily the npro- ofthe lith expensive article needed to produce an IC. You can start to see the utility together--the cess. It is, by design, massively parallel, such that tons of ICs are built up is the onlv wav ultimate assembly line efficiency. Think Henry Ford. This economy of scale are processing steps to build cheap ICs (hence, Moore's law), even though the individual very complicated and very costly. resist? Well. we use an So how then is the master mask used to produce a pattern in the Frightening optical projection lithography system (Figure 742). Sound expensive? It is! covered with resist,wave- complicated in practice but conceptually quite simple. A waferviais alaser of aj precise sharply then the mask is held above the wafer while UV light (usually images the the length) is shone through the mask and a series of lenses that focus from Chapterr 2want onto the wafer, exposing the resist to the light. Why UV? Well, recalltrying IfI tosee. smaller relation between the wavelength of the light and the object we are much have to expose a 1um' object in the resist, I better use light withha wavelength it will state-of-the-art otherwise than 1um (read: smaller than visible wavelengths of 0.4-0.7 um); in a deep fuzzy, washed-out edges (read: lith disaster), The typical light source andintense togo optical lith system is a Kr-F excimer laser, which can generate a pure played that can then be Bevond t ultraviolet (DUV) wavelength at 193 nm. Clever mask games masks). mOre even smaller geometries using optical projection (e.g,, phase-shifting optionbutto for patterning shapes doWn to, say, 10s of nanometers, one has no Bricks and Mortar: Micro/Nanoelectronics Fabrication 217 Electron gun Lens #1 Lens #2 Deflection coils Lens #3 Si wafer FIGURE 7.43 Representation of an electron-beam lithography system. (Inspired by Anderson, B.L. and Anderson, R.L., Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 2005.) much shorter wavelengths still for resist exposure, and the most common choice is to use electron-beam (e-beam) lithography, as depicted in Figure 743 (recall the discussion of using electrons for imaging in Chapter 2). Interestingly, there is no lith mask per se needed in e-beam lith, which might appear to be a huge cost advantage over optical lith. Alas, no, because the e-beam "write time" is far longer than that for optical systems, producing a lith-throughput bottleneck (the electron beam has to literally trace out each shape to be patterned, whereas in an optical system the whole die is exposed at one time). Still, e-beam lith is the gold standard for ultrafine-line nanoscale fabrication and is in use worldwide, especially in the research arena. GEEK TRIVIA: PHOTORESIST Interestingly enough, goodole William Shockley had his hand in the application of photolithog raphy to semiconductor manufacturing (6]. In the early 1950s, one of Shockley's highly capable assistants was a guy named Jules Andrus, who just happened to be a commercial artist by proies sion. In 1954,Shockley had a"crazy" (his words) idea about applying photoresistused in com mercial film photography to pattern shapes in transistors, and he sent Andrus to Eastman Kodak (think old-school Kodak camera film) in Rochester, NY, ona fact-finding mission. Aprototype lith technique was quickly and successíully applied to transistor íab, culminating in the famous Andrus patent, U.S. Patent 3,122,817, filed February 4, 1963, and issued March 3, 1967,* * Given all that I have told you about Shockley's personality, it is truly amazing that Shockley's name is not on this patent!  Microelectronics and Silicon Earth: Introduction to Nanotechnology 218 Enough of the history! So how exactly does photoresistwhen work? Most polymers (think exposedto UV light, with long strands of linked carbon-based molecules), increased molecular form "radh-plastics, calI species" that can result in polymer cross-linking and weight, altering their physical and chemical properties such that what was once easily dissolved in chemical A no longer dissolvesin chemical A(i.e., its so-called dissolution rate is changed). Whereas the inhibiting such automotive and aerospace industries focus aton of research on reactionsin order to extend the lifetime of plastic coatings on components, the lisemi ght-polconduc- ymer exploits these physical changes for the photoresist used in tor industry actively A"negative" lithography. resist becomes insoluble in the resist developer after it is exposed to UV light, whereas a"positive" resist becomes soluble (i.e., Ican either leave a hole in the resist where what is needed| for my intended image is or leave theimage itself, depending on mixture One very common positive UV photoresist is based on a of fabrication). diazonaphthoquinone (DNQ) and novolac resin (a phenol formaldehyde resin). DNQ inhibits the dissolution novolac resin. On UV exposure, however, the dissolution rate increases to even beyond that of pure novolac. DNQ-novolac resists are developed by dissolution in tetramethyl ammo nium hydroxide in water. DUV resists are typically polyhydroxystyrene-based polymers with a photoacid generator used to provide the requisite solubility change. Metalization and Interconnects All of these sophisticated wafer fab techniques would mean little at the end of the day if we didn't have a clever way to connect all of the pieces together. That is, it is one thing (a pretty big thing actually) to build 1,000,000,000 transistors on a centimeter-sized silicon die. But it is quite another to connect all 1,000,000,000 of those buggers together in some useful fashion (e.g., to build a microprocessor to serve as the brains of your laptop). This is where IC "interconnects" come intoplay. Think fancy point-to-point wiring. Figures 7+ and 745 show top-down and cross-sectional views of state-of-the-art interconnects used in microprocessors. In the 1970s, only 2 layersof interconnect were typically used; today, it is 8-14 layers, and growing. Simply put, with 1,000,000,000 transistors to connect up, this ver itable rat's nest of wires can be handled only by many independent layers. As a reminder, a centimeter-sized modern microprocessor literally has several MILES of micron-sized metal wires connecting up all its internal guts. With only amoment's reflection, you can convince yourself that these intercones are going to have to be made from metals. Why? Wel1, remember RC time constants from high school physics? No worries; let me remind you! Imagine that IIhave acapa want to move tor C that Iwant to charge up through aresistance to voltage V. That is, the voltage signal from point Ato point B. How long does that take? Well, trom n physics, this isan exponentialcharging process (determined by the differential equati governing the process-don't be frightened, no need to pull it out), and the charg capacitor) the the capacitor q builds (current flows) in time t (establishing the voltage on according to (71) q= CV( - et/R). Hence RC clearly has dimensions of time (the exponential function is dimensionless).orvoltage the smaller RC is, the faster we can charge the capacitor to the needed charge Bricks and Mortar: Micro/Nanoelectronics Fabrication 219 FIGURE 7.44 Top view of the copper metalization of amodern IC. (Courtesy of lnternational Business Machines Corporation, Armonk, NY) (this might represent our logical "1" for a digital bit moved from point A to point B). In fact, we can easily show that within one "RC time constant" the charge on the capacitor reaches (1 -e= 63%) of itsfinal value. Got it? Good. Now, let's assume that the length of the wire connecting two transistors is fixed, and hence the capacitance associated with the wire itself is fixed. Then, the smaller the R is of our wire, the faster Mr. (Ms.?) Transistor can talk to his/her neighbor (smaller RC time Constant). For a given geometry of the wire in question (length x width x height), the Smaller the resistivity of the wire material used to fab it, the smaller R will be. Materials with the smallest resistivity? Yep, metals! Okay, so what metal should we use? Historically, aluminum (AI) has dominated the IC interconnect business, at least until recently. Why? Low resistivity (2.65 uS2em: recall, a 220 Silicon Earth: Introduction to Microelectronics and M8 Nanotechnol gy M7 M6 M5 M4 M3 M2 MI FIGURE 7.45 A cross-sectional view of the eight different layers of metal interconnects on a 90 nm CMOS technology. From the bottom of metal layer 1 (M1) to the top of mnetal layer 8 (M8) is about 20 um, 20 millionths of a meter. (Courtesy of Intel Corporation, Santa Clara, CA) typical starting silicon wafer in IC fab might be 10 S2cm) and relatively easy to both depost and etch. So how do we build the interconnect? Well, first we blanket deposit a thin layer of Al across the entire wafer and then use lith to pattern the intended wire shape, to lowed by either wet or dry etching to remove the Al everywhere except where we wat t Need two layers of interconnect? Fine; just cover that first Al wire with chemica-vapor deposited dielectric, CMP it to planarize the surface, and now use lith again to pate a metal-to-metal contact point (called a "via"), etch the via, fillit up with another reference (typically tungsten [W], to form a W"stud" Sorry, no imaginative breeding intended; think stud in an earring), deposit the second metal layer, pattern it, and Done. We have Metal 1(M1) for "wire routing," Metal2 (M2) for independent wire to has M1 througn and the ability to connect M1 and M2 with a via, as needed. Figure 745 M8 and also shows metal-to-metal vias, along with clearevidence of CMP panm most thin-ilm How do we deposit the requisite Al? Evaporation is the classical path for vacuum our wafer inside a metal deposition. It may sound strange, but in essence, we put toits the metal chamber, pump it down, and then use an electron "beam" to heat upthe metal atoms vaporization temperature (i.e., create a vapor of metal atoms), and thenduring theevap not deposit themselves onto the surface of said wafer. We rotate the wafersmetals that mayWas ration process to ensure a uniform thickness (Figure 746). Done! For cannon"in Star violent evaporate well (e.g., W), we can use an argon ion beam (recall the "ion Alittle more Episode V: The Empire Strikes Back!)to"sputter" metals onto wafers. (Cu)not but the same idea. copper matter It turns out that state-of-the-art interconnects are actually built with itisalla Al-observe the copperish color of the metals in Figure 744. Why Cu? Well, i Rricks and Mortar: Micro/Nanoelectronics Fabrication 221 Si wafers Electron beam Crucible Aluminum vapor Molten aluminum Bell jar Vacuum Electron gun Power supply pump FIGURE 7.46 Representation of an e-beam evaporator for metal deposition. (Inspired by Anderson, B.L. and Anderson, R.L., Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 2005,) of resistivity. Al has a resistivity of 2.65 u2cm, but Cu has 1.70 uslcm, the best value of all easily accessible metals for IC manufacturing. Although this may seem like a modest improvement, it's not. During the 1990s, microprocessor designers already began to bump up against "interconnect delay" limits (7]. In essence, if the RC timeconstant of the wires in the "critical delay paths" is too large, and I am continuing to run the microprocessor faster and faster with each technology scaling advance, eventually I reach apoint where the IC speed is limited by the wiring delays and not the transistors, and hence the microproces sor just doesn't get any faster in going from scaling node A to scaling node B (say 180 to 90nm)major bummer since you just plopped down $10B for the 90 nm fab! Solution? Well, be you might say, "let's just make the Al wiresthicker, to lower their total resistance." You'd right, up to a point. The drawback is that the thicker the Alwires get, the farther apart they have to be placed (a transistor density hit), and the more problems with planarization I have to dealwith. Better solution? Change metals in my interconnects. For the same wire length and geometry, Ican get a36% improvement in interconnect delay just by moving from Al to Cu. See Head Scratcher #1 for a discussion of gold interconnects. Improved Cu resistivity is the upside (and it's a big upside). The downside is that it is VERY difficult to either wet or dry etch Cu, and this effectively held up progress on Cu interconnects until the late 1990s. Interestingly enough, to get around this, one actually electroplates Cu to aseed layer rather than depositing it and etching it away, as done with Al. In electroplating (an ancient process), an electrically conducive "seed layer" Is deposited and patterned, and then the wafer is immersed into the Cu plating solu tion and a DC bias applied between the Cu solution and the seed layer, resulting in Cu deposition (plating) on only the patterned seed layer. Today, we use a technique called a dual-Damascene process," which allows us to create both plated Cu interconnects and Cu-to-Cu vias (repeatedly) within the same fab sequence. The 90 nm BEOL shown in Figure 745 is done this way. One final thing regarding interconnects. One of the sinmplest ways to obtain a decent wiredirectly on the silicon wafer surface is to deposit a metal on the silicon and then give It agentle bake to cause a chemical reaction between the metal and silicon, producing a 222 Silicon Earth: Introduction to. Microelectronics and (Co), and tungsten "silicide." For example, titanium (Ti), cobaltCoSi, WSi). Silicides (W) are icides found in IC manufacturing (TiSi,, all Nanotec typically comMon have sil. hnol gy pure netals (e.g., TiSi,,= 25 sume silicon when they react; but advantageous, and are thus commonly iscm), poor resistivity compared with thatif ofused in only short or noncritical and they re do con used, inespecially lative terconnects, theyly can prove to be highly transistors to minimize resistive parasitics. INSIDE GOLD HEAD SCRATCHER #1: THE PRICE OF me a disadvantage associated Recently during a lecture | asked my students to tell with gold for metalization in IC manufacturing. A hand shot up"it is too expensive!" Ange using buzzer sounds. Nope, but thanks for playing! My interest piqued, I told the class that I would problem. Assuming u give some extra credit to the first student to solve the following to deposit a 1.0 cm long by 1.0 pm wide by 1.0 pm thick gold wire onto a silicon wafer what would be the cost of the gold required, assuming a current market price? Answer: 4) microcents per wafer! ($4.2 x 10-8!). Read: Cost is no big deal. Said another way, I could fk 23,809,523 such wafers before spending a buck for the gold! Not a hard problem, give ita disadvantace try! Question: So let me then ask you, gentle reader-What would in fact be a carrier and of using gold for metallization in silicon? Give up? Hint: It has to do with traps recombination (refer to Chapter 5). Building a Transistor Whew! Finally, we have arrived. Our fab toolkit is now complete, and we can actually build Mr. (Ms.?) Transistor and connect him/her up to do something useful. Con siaer Figures 7.47 and 7.48, which show cross-sectional images of modern high-speed ta tors. The first is a 130 nm SiGe heterojunction bipolar transistor (HBT) used in high-spe communications ICs, and the second is a 65 nm field-effect transistor (MOSFEl) Us ther Still, microprocessor applications. Both look pretty complex, and indeed they are. Disclaimer can be constructed by using the basic fab techniques previously outlined.and hundreds Building the transistors shown would actually require 30-35 lith masks book!), requr of individual processing steps (the fab "recipe" might take up half of this multi-billion-dollar ing say 1012 weeks of 24/7 effort by lots of folks in a state-of-the-art"bare-bones" pathto 300 mm facility. Read: What I am after is simply showing you a thisstut how all transistor fab, and this is intended only to give you a realistic feel for happens. Real life is always more complicated! top-downview + sequence So... let's build a transistor! Figure 749 shows a dual cross-sectional Construction together of the simplest possible transistor (a MOSFET), as a step-by-step Sequence, "tive Figure 7.50 liststhe "processflow" (what actually happens when) of the: calleda with the required lith mask levels. This MOSFET fab sequence would be MOSFETthatthent mask process" (requires five lith masks to make it). This is the sort ofhowtotbuild thelith universities will actually allow students to go into the lab and learn fancy, and how' selves during a one-semester course in micro/nano fabrication. Nothing illustrates will be coarse(maybe 5 im), but it will function as a transistor and it nicely fabrication works. Ahhh yes, education in action.  Fabricatioy Bricks and Mortar: Micro/Nanoelectronics 223 Dielectric E B C SiGe Tungsten STI N Collector Deep trench Oxide removed isolation NSubcollector PSubstrate FIGURE 7.47 Decorated cross-sectional view of amodern bandgap-engineered SiGe bipolar transistor. (Courtesy of International Business Machines Corporation, Armonk, NY.) 50nm FIGURE 7.48 Across-sectional view of aMOSFET from a 90 nm CMOS technology. The active transistor region is 50 nm, 50 billionths of a meter. (Courtesyof Intel Corporation, Santa Clara, CA.) Basic steps to building atransistor: Deposit dielectrics on the wafer surface, pattern them with lith t etching, and form the thick "field-oxide" isolation by thermaloxidation. Deposit n-type poly using LPCVD, and pattern the layer with lith +etching (this will be the MOSFET "gate").  Silicon Earth: Introduction to Microelectronics and Nanotechnol zy 224 Cross-sectional view Silicon nitride SiO, p-type silicon Top view of masks Boron (a) implant (b) Polysilicon SiO, SiO, p* (c) Dopant SiO, SiO, p* n (d) CVD SiO, SiO2 SiO, n (e) AJ 4-p (f) masksareshow FIGURE 7.49 Englew lithography Simplified cross-sectionalview of the step-by-step construction of a MOSFET. The Prentice-Hall, to the right (51. (Inspired by Jaeger, R.C., Introduction of Microelectronic Fabrication, Cliffs, NJ, 2002.) Rricks and Mortar: Micro/Nanoelectronics Fabrication 225 Fabrication flow Start Mask #2 Gate definition Thermal oxidation Source/drain CVD nitride deposition implantation Mask #1 Source/drain Active area definition diffusion CVD oxide Boron field implant deposition Mask #3 Contact openings Thermal field oxidation Remove nitride Metal deposition and oxide pad Mask #4 Pattern metal Regrow thin gate oxide Etch metal Boron threshold adjustment implant Mask #5 Passivation layer CVD polysilicon deposition' deposition Open bonding pads Finish FIGURE 7.50 Simplified step-by-step fabrication flow for building a MOSFET. (nspired by Jaeger, R.C, bntroduction of MicroelectronicFabrication, Prentice-Hall, Englewood Cliffs,NJ, 2002,)  Silicon Earth: Introduction to 226 Microelectronics and CMOScross-section Nanotechnol gy Solder bump Passivation 2 Passivation 1 Metal 4 Metal 3 Metal 2 Metal 1 W stud Cu 4Cu Metal 0: local interconnect nFET pFET Si wafer FIGURE 7.51 Schematic cross section of a four-layer metal CMOS IC. (Inspired by Anderson, B.L. and Anderson, K Fundamentals of Semiconductor Devices, McGraw-Hill, New York, 2005.) " Use ion implantation + rapid thermal annealing to form heavily n-type doped regions (this will be the MOSFET "source" and "drain" regions). Deposit CVD oxide on the wafer, pattern the contact openings, and etch them. etchit. Evaporate Al onto the wafer, and then use lith to pattern the metal (M1) and interconnect lavers Done! You could, of course, now begin to add additional metal on top of this first one, as needed, each obviously requiring additional ma processing. tour-laver simpleneededt Figure 7.51 shows a realistic (to scale) schematic cross-section of a metal CMOS technology (with both n-type and p-type MOSFET transistors mostofthe that build CMOS electronic circuits-atopic for the next chapter). Observeintterconnects. ln metal "over-layer" superstructure of a real CMOS technology resides in the to the top current-day CMOS technology, the distance from the silicon surface ofmavbe 0.5utl. is in the range of 15-20 um, compared with the transistor thickness isin metallaver. ofthe Figure 7.52 also shows the final steps for IC fab. Once the final top surtace top dependin; place, we deposit protective "passivation" layers (e.g., Si,N) on the finally, wafer, use lithto define and then etch "bond pad" windows, PbTi "'solderbumps aand, on the IC packaging required, follow that by the deposition of Bricks and Mortar: Micro/Nanoelectronics Fabrication 227 Wafer test and sort Dice wafer Die attach Wirebond Plastic encapsulant Final package and test FIGURE 7.52 Process flow from fabricated wafer through completed IC package. (Inspired by Jaeger, R.C., Introduction of Microelectronic Fabrication, Prentice-Hall, EngiewoodCliffs, NJ,2002.) (basically 100 um sized balls of solder, sometimes called "C4 balls"you'll see why these are handy in a moment). The IC is now complete. Finito! Piece of cake, right? Congratulations! You've just built your own transisto! ICPackaging: Wirebonds, Cans, DIPs, and Flip-Chips At this stage, Mr. (Ms.?) IC (containing 1,000,000,000 transistors), although dressed up and pretty, is still in wafer form (Figure 7.1). Read: not especially useful for sliding into your laptop or smartphone! IC packaging comes next;post-fab fab, as it were. When Isay IC "packaging," think of acontainer into which Iplace the IC that: (1) protects it from the world (e.g., our grubby fingers) and (2) provides an electrical means to get power (the applied voltage to run the circuit) and sigrnal lines (carrying "1s" and "0s") on and off the ICcleanly. This is actually pretty scary to think about. A modern microprocessor might lit erally have 100s of input-output (I/0) pins to deal with. Not surprisingly, IC packaging has evolved over time in its sophistication to handle the growing numbers of I/Osrequired to do business, and the IC package types around today are many and varied. Illintroduce you to some of the more common ones. First things first, though. We need to go from silicon wafer to silicon "die," that centime ter-sized silicon "microchip"(often just called a "chip"). How? Simply use a circular saw running at high rpms and literally saw up the wafer into pieces. Do make sure to first put them on a piece of blue two-sided sticky tape first so they don't fly all over the room. What kind of saw do we use? You guessed it--a diamond saw (the onlything that can cut silicon cleanly). First, however, we willelectrically test each IC (remember, there may be 100s per wafer) for functionality and identify with an ink-blot marker which ones work and which ones are dead (aka the IC yield). Yield for a mature CMOS technology should be in the >90% range (ifyou intend to stay in business). The functional IC die is then picked up by a robot and placed (literally referred toas a"pic-and-place" tool, go figure) into said pack age, attached with epoxy (uninspiringly, called 'die attach"), wirebonded (more on this 228 Silicon Earth: Introduction to Microelectronics and in a second), carefully sealed, typically and then retested to make sure all is well, a little with a rather boring sad finally sent to Company cured that black plastic is looking Xfor used to seal use in Nablnotaecckhno zpylastik. Y(Figure 7.52). To my mind it is Gizn because this hides the IC's good looks from lurking eyes, and hence most IC packags, have aclue what glory actually lies under the package cover. Sigh... Okay, the just don'folks does alsO protect isn't very the IC aesthetically from any appealing harmful (>ll light freely that admit might cause problems, I'm a sucker for those butblaalckas, plastr it jus phones and clocks that show all the gory guts). Some common package types? Well, for a single (discrete) For transistor, you se e-thmirogughht cel "can" package (no need to explain, look at Figure 7.53). DIP),6-40 pin ICs I use a "dual-inline" package (the famous and now-ubiquitous you might find in also shown in use 73 miFigghture a More sophisticated packages such as those your laptop or smartphone should you opt to pry off their covers (don't try this at home, kids) are DVD player or in Figure 7.54, and include the leadless chip carrier (LCC), the pin-grid array shown the ball-grid array (BGA). Remember, all lC packages do the same thing (protect t aand (PGA), provide electrical connections to the outside world), but these fancier packages allow higher pin counts than a typical DIP, for instance. So how does one connect the leads of a package to the fabricated IC? In one of ben ways, wirebonding or "flip-chip." Wirebonding is far more common today and still rath remarkable. Basically, a fancy sewing machine takes afine gold wire and fuses one end to a metalized pad on the package and then fuses the other end to the metal bond pad om the edge of theICthat might be only 100 um x 100 um in size (often smaller). This process is called "thermo-compression bonding," and the steps are illustrated in Figure 7.55, with the result shown in Figure 7.56. Look easy? Nope! First of ali, the Au wire is only15-75 um in diameter! For reference, atypical human hair is about 50 um in diameter. Go ahead. Can DIP Optical can Can Lead frame Die support paddle Si die Optical window Si die Wirebond Solder Header Insulator Lead (a) (b) wvirebon's FIGURE 7.53 (with package ICs Artech Schematic cut-away view of two popular types of packages used in low-integration-count(b)the "dual-in-line House shown):(a) the TO (transistor outline) "can," its close cousin the "optical can," and Bipolar Transistors, (DIP).(Unspired by Cressler, J.D. and Niu, G., Silicon-GermaniumHeterojunction Boston, MA, 2003.) Bricksand Mortar: Micro/Nanoelectronics Fabrication 229 Dual in-line package (DIP) Pin-grid array (PGA) Bottom of PGA Leadless chip carrier (LCC) Plastic leaded chip carrier (PLCC) Thin small-outline package (TSOP) Ball-grid array Bottom of BGA (BGA) FIGURE 7.54 A variety of IC packages that support much higher circuit integration levels. The DIP and pin-grid array (PGA) packages are "through-hole mount" packages (the ICs leads stick through the PCB and are soldered on the back side), whereas the rest are "surface-mount" packages (the IC is soldered to the surface of the PCB). (Inspired by Cressler, J.D. and Niu, G, Silicon-Germanium Heterojunction Bipolar Transistors, Artech House, Boston, MA, 2003.) pullone out right now and take alook; and then imagine using it in yourMom's sewing machine to sew a vest for a flea! You get the idea. AND, the wirebonding machine is going to execute in the range of 10bonds per second,24/7, yielding thousands of IC packages a day. Nope, definitely not easy. Flip-chip is just what it says.On the die, open the bond pads and then deposit solder balls (Figures 7.57 and 7.58). Now flip the chip upside down (hence the name), align it to the metal pads on the package, and gently heat it so that the solder ball fuses to the pack age. Done. Why bother? Well, several reasons: (1) Using flip-chip, I can populate solder balls literally all over the surface of the IC, not just around the edges, so the pin dernsity can be very high indeed, and (2) flip-chip is especially useful for minimizing the parasitics associated with the connection. That is, in aclassical wirebond, the parasitic inductance and resistance of the gold bond wire itself, although tiny, are actually large enough to cause major headaches for high-speed circuits (especially RF circuits; think smartphones).  Silicon Earth: Introductionto 230 Microelectronics and Capillary Wire bonding Nanotechnol Gold wire Heat source (a) (b) Si die Package substrate Substrate Wire (c) (d) tail end Substrate (e) () Top view FIGURE 7.55 Illustration of the wirebonding process. This case shows "thermosoic ball bonding." (Inspired by Jaeger.RC. Introduction of Microelectronic Fabrication,Prentice-Hall, EnglewoodCliffs, NJ, 2002.) Flip-chip essentially eliminates these parasitics, because the electrical path length is nv 100s of microns instead ofthe several millimeters in wirebonding. Although it tok ti chip packaging some time to catch on because of the complexity involved (you mignt a yourself, for instance, how one orients the solder balls on the upside-down die to the pat high-spet on the package-think mirrors!), flip-chip represents the gold standard in high-pin-count IC packaging we wantto integrat Okay, so now we have the IC packaged. What's next? Well, finallymultiple optionsThink the packaged IC into a useful electronic system, and again we have ICpackage of the PCB as a second level of packaging that can now accommodate multiple packages.Many and has its own lith-defined wiring to connect up all the I/Os of the various etc,)haveaPC3 common electronic products (e-g., laptop, smartphone, iPad, digital camera, eitherone can be attached to packa "motherboard," as shown in Figure 7.59, In this case, ICs "'surface--mount" even both sides of the PCB. In this case the IC packages utilize "chip-on-ban ing technology (just what it says). Asecond packaging approach is calledfollowedbyadt wirebonded, thecir (CoB), in which the bare die is attached to the PCB, and then needed to build whichhas be tional passive components (resistors, capacitors, etc) that might module (MCM), (Figure Zel cuit (Figure 760). Alogical extension of CoB is the multichip multiplelavets "'substrate" various bare die and passive components attached to a packaging cat deensitr substrate with independrt Importantly, in MCM, you can also build up the package levels of wiring (even 10-20 layers) of metal interconnects, such that very high thefuture? own Sur' Serves as its be achieved in atiny package. In MCM, the package substrate into interconnect platformn. What comes next? Well, how about a glimpse Bricksand Mortar: Micro/Nanoelectronics Fabrication 231 Spot Mag FWDE-Beam Tilt Det HEW 50 um 3 L20 kX4.963 5.00 kV 60.0 SED 253 um FIGURE 7.56 Decorated view of a single gold wirebond on the surface of an IC. (Courtesy of International Business Machines Corporation, Armonk, NY.) Package pin Package substrate Via Metal interconnection Solder bump Silicon chip on bonding pad FIGURE 7.57 atonof "lip-chip" package using solder bumps (aka C4 balls) on top of the contact pads. (lnspired by JaCger, kC, iniroductionof MicroclecirontcFabrication, Prentice-Hall, Englewood Clifs, N), 2002) 232 Silicon Earth: Introduction to Microelectronics and ICPackaging Nanotechnol gy Leads Pins 7ICpackage Printed circuit board Edge connector PCB System assembly System board FIGURE 7.58 Assembly flow from package to board to system. (Inspired by Fabrication, Prentice-Hall, Englewood Cliffs, NJ, Jaeger, R.C., Introduction of Microelectronic 2002.) R58T1 LRS9 TDAT517P 19436 c79| YSHS937 3 Y C68 c70 C74 R40 92S029 EC5C58 c C78 FIGURE 7.59 Aurora.WE) Actual PCBwith surface-mount IC packages attached. (Courtesy of International Sensor Systems,