Computer Architecture and Organization Lecture Notes PDF

Addis Ababa Science and Technology University Department of Electrical & Computer Engineering Computer Architecture and Organization Lecture by: Netsanet Getnet 1  1. INTRODUCTION Organization and Architecture Structure and Function...

Addis Ababa Science and Technology University Department of Electrical & Computer Engineering Computer Architecture and Organization Lecture by: Netsanet Getnet 1  1. INTRODUCTION Organization and Architecture Structure and Function Computer Evolution and Performance 2  Organization and Architecture Computer architecture refers to those attributes of a system visible to a programmer (or those attributes that have a direct impact on the logical execution of a program). Examples of architectural attributes: the instruction set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory. 3  Organization and Architecture (2) Computer organization refers to the operational units and their interconnections that realize the architectural specifications. Examples of organizational attributes: hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used. 4  Organization and Architecture (3) For example, it is an architectural design issue whether a computer will have a multiply instruction. It is an organizational issue whether that instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. The organizational decision may be based on the anticipated frequency of use of the multiply instruction, the relative speed of the two approaches, and the cost and physical size of a special multiply unit. 5  Structure and Function Structure: The way in which the components are interrelated. Function: The operation of each individual component as part of the structure. In general terms, there are only four functions: Data processing Data storage Data movement Control 6  Fig. 1.1: A Functional View of the Computer 7  Fig 1.2a. Data movement: Fig 1.2b Data storage: data transferred transferring data from one from the external environment to peripheral or communication computer storage (read) and vice versa 8 line to another. (write).  Fig 1.2c. Data processing, Fig 1.2d. Data processing, on data on data in Storage. en route between storage and the 9 external environment.  Structure Fig 1.3. The simplest possible depiction of a computer. 10  Structure (2) There are four main structural (internal) components: Central processing unit (CPU): Controls the operation of the computer and performs its data processing functions; often simply referred to as processor. Main memory: Stores data for the processor. I/O: Moves data between the computer and its external environment. System interconnection: Mechanism that provides for communication among CPU, main memory, and I/O. A common example of system interconnection is by means of a system bus, consisting of a number of conducting wires to which all the other components attach. There may be one or more of these components Examples uniprocessor/multiprocessor 11  Structure (3) The most interesting and the most complex component is the CPU. Its major structural components are: Control unit: Controls the operation of the CPU and hence the computer. Arithmetic and logic unit (ALU): Performs the computer’s data processing functions. Registers: Provides storage internal to the CPU. CPU interconnection: Some mechanism that provides for communication among the control unit, ALU, and registers. 12  Fig 1.4. The Computer: Top-Level Structure 13  Performance and Evolution Reading Assignment: Evolution THE VON NEUMANN MACHINE Suppose a program could be represented in a form suitable for storing in memory alongside the data. Then, a computer could get its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory. 14  Performance and Evolution (2) This idea is known as the stored-program concept, is usually attributed to the mathematician John von Neumann. In 1946, von Neumann and his colleagues began the design of a new stored program computer, referred to as the IAS computer, at the Princeton Institute for Advanced Studies. The IAS computer, although not completed until 1952, is the prototype of all subsequent general-purpose computers. 15  Performance and Evolution (3) Fig. 1.6. Structure of the IAS Computer (compare to middle part in slide 16 13)  Performance and Evolution (4) The IAS computer consists of A main memory, which stores both data and instructions An arithmetic and logic unit (ALU) capable of operating on binary data A control unit, which interprets the instructions in memory and causes them to be executed Input/output (I/O) equipment operated by the control unit 17  Performance and Evolution (5) With rare exceptions, all of today’s computers have this same general structure and function and are thus referred to as von Neumann machines. The memory of the IAS consists of 1000 storage locations, called words, of 40 binary digits (bits) each. Both data and instructions are stored there. Numbers are represented in binary form, and each instruction is a binary code. Figure 1.7 below illustrates these formats. 18  Performance and Evolution (6) Fig. 1.7. IAS Memory Formats A word may also contain two 20-bit instructions, with each 19 instruction consisting of:  Performance and Evolution (7) an 8-bit operation code (opcode) specifying the operation to be performed, and a 12-bit address designating one of the words in memory (numbered from 0 to 999). The control unit operates the IAS by fetching instructions from memory and executing them one at a time. Both the control unit and the ALU contain storage locations, called registers, defined as follows: Memory buffer register (MBR): Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit. 20  Performance and Evolution (8) Memory address register (MAR): Specifies the address in memory of the word to be written from or read into the MBR. Instruction register (IR): Contains the 8-bit opcode instruction being executed. Instruction buffer register (IBR): Employed to hold temporarily the righthand instruction from a word in memory. Program counter (PC): Contains the address of the next instruction pair to be fetched from memory. Accumulator (AC) and multiplier quotient (MQ): Employed to hold temporarily operands and results of ALU operations. For example, the result of multiplying two 40-bit numbers is an 80-bit number; the most significant 40 bits are stored in the AC and the least significant in the MQ. 21  Fig. 1.8. Expanded Structure of IAS Computer 22  Performance and Evolution (9) The IAS operates by repetitively performing an instruction cycle, as shown in Fig. 1.9. Each instruction cycle consists of two subcycles. The fetch cycle The execute cycle During the fetch cycle, the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the MBR, and then down to the IBR, IR, and MAR. 23  Performance and Evolution (10) Once the opcode is in the IR, the execute cycle is performed. Control circuitry interprets the opcode and executes the instruction by sending out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU. The IAS computer had a total of 21 instructions, which are listed in Table 1.1. These can be grouped as follows: Data transfer: Move data between memory and ALU registers or between two ALU registers. 24  Performance and Evolution (11) Unconditional branch: Normally, the control unit executes instructions in sequence from memory. This sequence can be changed by a branch instruction, which facilitates repetitive operations. Conditional branch: The branch can be made dependent on a condition, thus allowing decision points. Arithmetic: Operations performed by the ALU. Address modify: Permits addresses to be computed in the ALU and then inserted into instructions stored in memory. This allows a program considerable addressing flexibility. 25 Fig. 1.9. Expanded Structure of IAS Computer 26 27 The IAS Instruction Set  Performance and Evolution (12) Each instruction must conform to the format of one on slide 19. The opcode portion (first 8 bits) specifies which of the 21 instructions is to be executed. The address portion (remaining 12 bits) specifies which of the 1000 memory locations is to be involved in the execution of the instruction. Note that each operation requires several steps. Some of these are quite elaborate. The multiplication operation requires 39 suboperations, one for each bit position except that of the sign bit. 28 Computer System Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals What is a program? A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed Function of Control Unit For each operation a unique code is provided e.g. ADD, MOVE A hardware segment accepts the code and issues the control signals We have a computer! Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out Input/output Temporary storage of code and results is needed Main memory Computer Components: Top Level View Instruction Cycle Two steps: Fetch Execute Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions Execute Cycle Processor-memory data transfer between CPU and main memory Processor I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations e.g. jump Combination of above Example of Program Execution 0001 Load AC from memory 0010 Store AC to memory 0101 Add to AC from memory Instruction Cycle State Diagram Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O from I/O controller Hardware failure e.g. memory parity error Program Flow Control Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program Transfer of Control via Interrupts Instruction Cycle with Interrupts Program Timing: Short I/O Wait Program Timing: Long I/O Wait Instruction Cycle (with Interrupts) - State Diagram