Caalp mid-2 objectives.docx

**Unit-III:** 1.The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to \(A) the time it takes for the platter to make a full rotation \(B) the time it takes for the read-write head t...

**Unit-III:** 1.The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to \(A) the time it takes for the platter to make a full rotation \(B) the time it takes for the read-write head to move into position over the appropriate track \(C) the time it takes for the platter to rotate the correct sector under the head \(D) none of the above Ans: A 2\. What characteristic of RAM memory makes it not suitable for permanent storage? \(A) too slow (B) unreliable (C) it is volatile (D) too bulky Ans: C 3\. The circuit used to store one bit of data is known as \(A) Register (B) Encoder (C) Decoder (D) Flip Flop Ans :d 4\. The average time required to reach a storage location in memory and obtain its contents is called the \(A) seek time (B) turnaround time (C) access time (D) transfer time Ans: C 5\. The idea of cache memory is based \(A) on the property of locality of reference (B) on the heuristic 90-10 rule (C) on the fact that references generally tend to cluster (D) all of the above Ans: A 6\. If memory access takes 20 ns with cache and 110 ns with out it, then the ratio ( cache uses a 10 ns memory) is \(A) 93% (B) 90% (C) 88% (D) 87% Ans: B 7\. Cache memory acts between \(A) CPU and RAM (B) RAM and ROM (C) CPU and Hard Disk (D) None of these Ans: A 8\. Write Through technique is used in which memory for updating the data \(A) Virtual memory (B) Main memory \(C) Auxiliary memory (D) Cache memory Ans: D 9\. Generally Dynamic RAM is used as main memory in a computer system as it \(A) Consumes less power (B) has higher speed (C) has lower cell density (D) needs refreshing circuitary Ans: B 10\. Virtual memory consists of \(A) Static RAM (B) Dynamic RAM (C) Magnetic memory (D) None of these Ans: A 11\. Virtual memory consists of \(A) Static RAM (B) Dynamic RAM (C) Magnetic memory (D) None of these Ans: A 12\. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be \(A) 11 bits (B) 21 bits \(C) 16 bits (D) 20 bits Ans: C 13\. Cache memory works on the principle of (A)Locality of data (B)Locality of memory (C)Locality of reference D)Locality of reference & memory Ans: C 14\. The main memory in a Personal Computer (PC) is madeof (A)cache memory. (B)static RAM (C)Dynamic Ram (D)both (A)and (B). Ans: D 15\. Memory unit accessed by content is called \(A) Read only memory (B) Programmable Memory (C) Virtual Memory D) Associative Memory Ans: D **16.**  The advantage of memory mapped I/O over I/O mapped I/O is, \[    \] \(A) Faster (B) Many instructions supporting memory mapped I/O \(C) Require a bigger address decoder (D) All the above **UNIT IV**  1.Which of the following register is not present in EU( Execution Unit) of the 8086 microprocessor? \[   d\] a\. SP b.BP c.SI d.IP 2.  Which signal is used to demultiplex the Adress bus of 8086 \[   d  \] a\. BHE b.LOCK c.READY d.ALE 3.  Which of the following signal is used to control the direction of dataflow of bus transcievers \[  a \] \_ \_\_ \_\_\_\_ a.   DT **/** R b. M / IO c. DEN d.ALE 4.  Which of the following signal belongs to maximum mode only \[  c  \] \_\_\_\_ \_\_\_\_\_ \_\_\_\_\_ \_\_\_\_ a.   RD b. TEST c. LOCK d. DEN 5.  Which of the following pair of registers is invalid \[ a \] a\. CS:SP b. SS: SP c. DS:BX d. ES:DI 6.  Which of the following flags is used for single stepping \[   c\] a\. Direction Flag b. Interrupt Flag c. Trap Flag d. Overflow Flag 7.  Which of the following are the three basic sections of a microprocessor unit? \[   b\] \(A) operand, register, and arithmetic/logic unit (ALU) \(B) control and timing, register, and arithmetic/logic unit (ALU) \(C) control and timing, register, and memory \(D) arithmetic/logic unit (ALU), memory, and input/output 8.  Which bus is a bidirectional bus? \[  b \] \(A) address bus (B) data bus (C) address bus and data bus (D) none of the above 9.  Direction flag is used with \[  a\] \(A) String instructions (B) Stack instructions \(C) Arithmetic instructions (D) Branch instructions 10.  What does microprocessor speed depends on? \[  c \] \(A) Clock (B) Data bus width (C) Address bus width (D)size of register 11.  A register capable of shifting its binary information either to the right or the left is called a\[ c\] (A)parallel register (B) serial register (C) shift register (D) storage register 12.  What is meant by Mask able interrupts? \[  b \] \(A) An interrupt which can never be turned off \(B) An interrupt that can be turned off by the programmer \(C) An interrupt which can be turned off automatically \(D) none 13.  In a DMA write operation the data is transferred \[  a\] \(A) from I/O to memory (B) from memory to I/O \(C) from memory to memory (D) from I/O to I/O **UNIT 5** +-----------------------------------+-----------------------------------+ | 1 | 1\. \_\_\_\_\_\_ have been | | | developed specifically for | | | pipelined systems.\ | | | a) Utility software\ | | | b) Speed up utilities\ | | | c**) Optimizing compilers**\ | | | d) None of the mentioned | +===================================+===================================+ | 2 | The pipelining process is also | | | called as \_\_\_\_\_\_\ | | | a) Superscalar operation\ | | | b) **Assembly line operation**\ | | | c) Von Neumann cycle\ | | | d) None of the mentioned | +-----------------------------------+-----------------------------------+ | 3 | The fetch and execution cycles | | | are interleaved with the help of | | | \_\_\_\_\_\_\_\_\ | | | a) Modification in processor | | | architecture\ | | | b**) Clock**\ | | | c) Special unit\ | | | d) Control unit | +-----------------------------------+-----------------------------------+ | 4 | Each stage in pipelining should | | | be completed within | | | \_\_\_\_\_\_\_\_\_\_\_ cycle.\ | | | a) **1**\ | | | b) 2\ | | | c) 3\ | | | d) 4 | +-----------------------------------+-----------------------------------+ | 5 |  To increase the speed of memory | | | access in pipelining, we make use | | | of \_\_\_\_\_\_\_\ | | | a) Special memory locations\ | | | b) Special purpose registers\ | | | c) **Cache**\ | | | d) Buffers | +-----------------------------------+-----------------------------------+ | 6 | ** Pipelining is a | | | \-\-\-\-\-\-\-\-\-\-\--technique? | | | ** | | | | | | A.Serial operation | | | | | | B.**Parallel operation** | | | | | | C.Scalar operation | | | | | | D.Superscalar operation | +-----------------------------------+-----------------------------------+ | 7 | Consider the multiplication of | | | two 5 X 5 matrices using a vector | | | processor. How many product terms | | | are there in each inner product? | | | | | | (a) 10 | | | --------- ------- | | | (b) 6 | | | (c) 25 | | | **(d)** **5** | +-----------------------------------+-----------------------------------+ | **** | Which of the following is a type | | | of array processors? | | | | | | (a) Super array processor | | | ----- ------------------------- | | | - | | | (b) MISD array processor | | | (c) **SIMD array processor** | | | (d) All of above | +-----------------------------------+-----------------------------------+ | **** | Full-form of PE in SIMD array | | | processor? | | | | | | (a) Pipeline Enable | | | ----- ------------------------ | | | (b) **Processing Element** | | | (c) Priority Enable | | | (d) Primary Execution | +-----------------------------------+-----------------------------------+ | **** | Full-form of SIMD is \-\-\-- | | | **Single instruction stream and | | | multiple data stream** | +-----------------------------------+-----------------------------------+ | **** | An SIMD \_\_**Array | | | processor**\_\_\_\_\_\_\_\_ a | | | processor that has single | | | instruction multiple data | | | organization | +-----------------------------------+-----------------------------------+ | **** | A Measure use to evaluate | | | computers in their ability to | | | perform a given number of | | | floating point operation per | | | second is called as | | | \-\-\-\-\--**FLOPS** | +-----------------------------------+-----------------------------------+ | **** | How many types of | | | multiprocessors?\ | | | A. **2**\ | | | B. 3\ | | | C. 4\ | | | D. 5 | +-----------------------------------+-----------------------------------+ | **** |  Which of the following is | | | Disadvantages of Multiprocessor | | | Systems?\ | | | A. Multiprocessor systems is | | | quite expensive\ | | | B. All the processors in the | | | multiprocessor system share the | | | memory. So a much larger pool of | | | memory is required as compared to | | | single processor systems.\ | | | C. more complex and complicated | | | operating system is required in | | | multiprocessor systems.\ | | | **D. All of the above** | +-----------------------------------+-----------------------------------+ | **** | Which processor requires more | | | number of registers? | | | | | | A. CISC\ | | | B. ISA\ | | | C**. RISC**\ | | | D. ANNA | +-----------------------------------+-----------------------------------+ | **** | +------------------------------+ | | | | Which two pipelines (in | | | | | proper sequence) are used to | | | | | calculate an inner product | | | | | in vector processor? | | | | | | | | | | (a) **Multiplier pipelin | | | | | e, Adder pipeline** | | | | | ----- -------------------- | | | | | ---------------------- | | | | | (b) Multiplier pipeline, | | | | | Subtractor pipeline | | | | | (c) Adder pipeline, Mult | | | | | iplier pipeline | | | | | (d) Subtractor pipeline, | | | | | Multiplier pipeline | | | | +------------------------------+ | +-----------------------------------+-----------------------------------+ | **** | The term \_\_\_\_\_\_ is used to | | | denote billion flops. | | | | | | (a) megaflops | | | ----- --------------- | | | (b) **gigaflops** | | | (c) kiloflops | | | (d) teraflops | +-----------------------------------+-----------------------------------+ | **** | Zero Address Instruction | | | | | | A. RISC architecture | | | | | | B. CISC architecture | | | | | | C. Von-Neuman architecture | | | | | | D. S**tack-organized | | | architecture** | +-----------------------------------+-----------------------------------+ | **** | Which multiprocessor system | | | contain a master slave | | | relationship | | | | | | A. Symmetric Multiprocessor | | | | | | B. Singlton Multiprocessor | | | | | | C. **Asymmetric Multiprocessor** | | | | | | D. Both A and B | +-----------------------------------+-----------------------------------+ | **** | A multiprocessor operating system | | | must take care of | | | | | | A. **Unauthorized data access and | | | data protection** | | | | | | B. Authorized data access and | | | data protection | | | | | | C. Authorized data access | | | | | | D. Data protection | +-----------------------------------+-----------------------------------+