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BECE102L-Digital Systems Design Mod-5 DESIGN OF SEQUENTIAL LOGIC CIRCUITS Course Instructor Dr. Penchalaiah Palla Department of Micro and Nanoelectronics School of Electronics Engineering Vellore Institute of Technology Vellore, TN ...

BECE102L-Digital Systems Design Mod-5 DESIGN OF SEQUENTIAL LOGIC CIRCUITS Course Instructor Dr. Penchalaiah Palla Department of Micro and Nanoelectronics School of Electronics Engineering Vellore Institute of Technology Vellore, TN Introduction:Sequential Circuits ◆ Combinational The outputs depend only on the current input values It uses only logic gates ◆ Sequential The outputs depend on the current and past input values It uses logic gates and storage elements Example ✓ Vending machine They are referred as finite state machines since they have a finite number of states 5 Block Diagram ◆ Memory elements can store binary information This information at any given time determines the state of the circuit at that time 6 ▪ A sequential circuit consists of a feedback path, and employs some memory elements. Combinational outputs Memory outputs Combinational Memory logic elements External inputs Sequential circuit = Combinational logic + Memory Elements Sequential Circuit Types ◆ Synchronous The circuit behavior is determined by the signals at discrete instants of time The memory elements are affected only at discrete instants of time A clock is used for synchronization ✓ Memory elements are affected only with the arrival of a clock pulse ✓ If memory elements use clock pulses in their inputs, the circuit is called Clocked sequential circuit ◆ ASynchronous The circuit behavior is determined by the signals at any instant of time It is also affected by the order the inputs change 8  IN short…….. ▪ There are two types of sequential circuits: ❖ synchronous: outputs change only at specific time ❖ asynchronous: outputs change at any time ▪ Multivibrator: a class of sequential circuits. They can be: ❖ bistable (2 stable states) ❖ monostable or one-shot (1 stable state) ❖ astable (no stable state) ▪ Bistable logic devices: latches and flip-flops. ▪ Latches and flip-flops differ in the method used for changing their state.  Latches & Flip-flops ▪ Memory Elements ▪ Pulse-Triggered Latch ❖ S-R Latch ❖ Gated S-R Latch ❖ Gated D Latch ▪ Pulse-Triggered Flip-Flops(Level Triggered) ❖ Master-Slave Flip-flops ▪ Edge-Triggered Flip-flops ❖ S-R Flip-flop ❖ D Flip-flop ❖ J-K Flip-flop ❖ T Flip-flop ▪ Asynchronous Inputs Memory Elements ▪ Memory element: a device which can remember value indefinitely, or change value on command from its inputs. Memory Q command element stored value ▪ Characteristic table: Command Q(t) Q(t+1) (at time t) Q(t): current state Set X 1 Q(t+1) or Q+: next state Reset X 0 Memorise / 0 0 No Change 1 1 Memory Elements ▪ Memory element with clock. Flip-flops are memory elements that change state on clock signals. Memory Q command element stored value clock ▪ Clock is usually a square wave. Positive pulses Positive edges Negative edges  Clock Edges Positive Edge Transition 1 0 1 0 Negative Edge Transition 13 Memory Elements ▪ Two types of triggering/activation: ❖ pulse-triggered ❖ edge-triggered ▪ Pulse-triggered ❖ latches ❖ ON = 1, OFF = 0 ▪ Edge-triggered ❖ flip-flops ❖ positive edge-triggered (ON = from 0 to 1; OFF = other time) ❖ negative edge-triggered (ON = from 1 to 0; OFF = other time) Flip-Flops ◆ They are memory elements ◆ They can store binary information Clock: ◆ It emits a series of pulses with a precise pulse width and precise interval between consecutive pulses ◆ Timing interval between the corresponding edges of two consecutive pulses is known as the clock cycle time, or period 15 Flip-Flops ◆ Can keep a binary state until an input signal to switch the state is received ◆ There are different types of flip-flops depending on the number of inputs and how the inputs affect the binary state 16 Latches ◆ The most basic flip-flops They operate with signal levels ◆ The flip-flops are constructed from latches ◆ They are not useful for synchronous sequential circuits ◆ They are useful for asynchronous sequential circuits 17  Summary: Memory Elements Allow sequential logic design Latch — a level-sensitive memory element SR latches D latches Flip-Flop — a clocked 1-bit memory element Master-slave flip-flop Edge-triggered flip-flop RAM and ROM — a mass memory element SENSE Sequential Circuits 18  Summary: Sequential Networks The logic networks studied so far are combinational networks: – The outputs at any instant depend only upon the inputs present at that instant. Sequential Network: – The outputs at any instant are dependent not only upon the inputs present at that instant but also upon the past history of inputs. Sequential networks have memory. – The information preserved is referred to as the internal state, secondary state, or state of the network.  Summary: Sequential Networks Synchronous sequential network – Behavior is determined by the values of the signals at only discrete instants of time. – Master-clock generator which produces a sequence of clock pulses that sample the input. Asynchronous sequential network – Behavior of the network is immediately affected by the input signal changes.  Flip-Flop The basic logic element that provides memory in many sequential networks. Flip-flop itself is a simple sequential network. – All sequential networks require the existence of feedback. – Feedback is present in flip-flop circuits. Flip-flop has two stable conditions. – Each of this is associated with a state or storage of a binary symbol.  The Basic Bistable Element Central to all flip-flop circuits. Has two outputs 𝑄, 𝑄 Two stable states: – 𝑥 = 0; 𝑥 = 1; 𝑄 = 1; 𝑦 = 1; 𝑦 = 0; 𝑄 = 0; 𝑥 = 0; 𝑄 = 𝑥 = 𝑦 = 0; 𝑄 = 𝑥 = 𝑦 = 1 – 𝑥 = 1; 𝑥 = 0; 𝑄 = 0; 𝑦 = 0; 𝑦 = 1; 𝑄 = 1; 𝑥 = 1; 𝑄 = 𝑥 = 𝑦 = 1; 𝑄 = 𝑥 = 𝑦 = 0  The Basic Bistable Element When output line 𝑄 = 1 the element is storing a 1; when output line 𝑄 = 0 the element is storing a 0. There is one more equilibrium condition that can exist. Occurs when the two output signals are halfway between logic-0 and logic-1. Known as metastable state. – Any small change causes the element to enter one of its two stable states. – Amount of time a device can stay in its metastable state is unpredictable. – Metastable state must be avoided.  The Basic Bistable Element Has no inputs. When power is applied, it becomes stable in one of its two stable states and remains in this state until power is removed. To be useful, must be able to force the device into a particular state. A flip-flop is a bistable device, with inputs, that remains in a given state as long as power is applied and until input signals are applied to cause its output to change. Inputs to flip-flops: – Asynchronous or direct input: a signal change produces an immediate change in the state of the flip-flop. – Synchronous input: A signal change does not immediately affect the state of the flip-flop. Affects it only when some control signal (clock) occurs.  Latches Latches are one class of flip-flops The timing of the output changes is not controlled – The output responds immediately to changes on the input lines. – Input lines are continuously being interrogated. Sections 6.4,6.5: flip-flops in which the timing of the output changes is controlled.  The SR (set-reset) Latch Cross-coupling of two NOR gates. Two inputs: S, R referred to as the set and reset inputs Two outputs: 𝑄, 𝑄 S = R = 0 logic diagram simplifies to basic bistable element R = 1; S = 0—latch is “reset” If R is returned to 0 then latch retains its present state S = 1; R = 0—latch is “set” S,R are asynchronous inputs  The SR (set-reset) Latch Cross-coupling of two NOR gates. Two inputs: S, R referred to as the set and reset inputs Two outputs: 𝑄, 𝑄 Consider the case where S = R = 1 – Output of both NOR gates becomes 0, not complementary When inputs return to 0: – If one input returns to 0 before the other, the last input to stay at 1 determines the final state. – If both inputs return to 0 simultaneously, the device may enter its metastable state. Final state is unpredictable. S = R = 1 regarded as “forbidden state”  Next state is the The SR Latch same as the previous state. + 𝑄+ , 𝑄 indicates the response of the latch at the 𝑄, 𝑄 output terminals as a consequence of applying the various inputs. 𝑄+ is called the next state of the latch.  The 𝑆 𝑅 Latch Cross-coupling of two nand-gates When 𝑆 = 𝑅 = 1 logic diagram reverts to the basic bistable element. Device has 2 stable states.  The Gated SR Latch Inputs for SR Latch and 𝑆 𝑅 Latch are asynchronous. – A change in the value of the inputs causes an immediate change of the outputs. Frequently desirable to prevent input activation signals from affecting the state of the latch immediately. “gated SR latch” or “SR latch with enable” is used.  The Gated SR Latch 𝑆 𝑅 Latch along with 2 additional NAND gates and a control input C. – C is referred to as enable, gate or clock input. C determines when the S and R inputs become effective. As long as C input is 0, outputs of NAND gates are 1, keeps the 𝑆 𝑅 Latch in its current stable state. – Any changes to S,R are blocked. – Output is “latched” in its present state. When C is 1, the latch behaves as an SR Latch. If S = R = C = 1 then 𝑄 = 𝑄 = 1. – If C then goes to 0, can enter metastable state. The Gated SR Latch  The Gated D Latch The latches discussed thus far each has an input combination that is not recommended. The gated D (data) latch does not have this problem. Gated SR-latch in which a not-gate is connected between the S and R terminals. Why does this help? The Gated D Latch  Timing Considerations Responses to inputs are not really immediate, but occur after some appropriate time delay. To achieve desired responses, certain timing constraints must be satisfied.  Propagation Delays The propagation delay is the time it takes a change in an input signal to produce a change in an output signal. Propagation delay from low to high: 𝑡𝑝𝐿𝐻 In general, these may be Propagation delay from high to low: 𝑡𝑝𝐻𝐿 different.  Timing Diagram Propagation delays from high-low, low-high assumed equal. When S = R = 1, both 𝑄, 𝑄 become 0. 𝑡15 , signals on S, R are simultaneously changed from 1 to 0. – Response of latch is unpredictable. Can be in 0-state, 1-state or metastable state. – Application of 1 on the set input terminal returns the latch to predictable.  Minimum Pulse Width Another specification stated by the manufacturers of latches is that of a minimum pulse width 𝑡𝑤(𝑚𝑖𝑛). – Minimum amount of time a signal must be applied in order to produce a desired result. Failure to satisfy the constraint may cause unintended change or have the latch enter its metastable state.  Setup and Hold Times Consider timing diagram for a gated D latch Q-output follows the input signal at D whenever the enable signal C = 1. When C = 0, changes are ignored. Consider times 𝑡3 , 𝑡6 , 𝑡11 , 𝑡14. – C is returned to 0. Output latches onto its current state. – To guarantee latching action: constraint is placed on D signal. Must not change right before and after C goes from 1 to 0. Setup time: minimum time 𝑡𝑠𝑢 that D signal must be held fixed before the latching action. Hold time: minimum time 𝑡ℎ that D signal must be held fixed after the latching action. Unpredictable Response in a gated D latch  Symbols for Latches D latch with asynchronous reset always @(reset or data or gate) if (reset) q = 1’b0; else if (enable) q = data; SENSE Sequential Circuits 41 42 Latch Circuits: Not Suitable ▪ Latch circuits are not suitable in synchronous logic circuits. ▪ When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output. ▪ The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change. ▪ This leads us to the Pulse and edge-triggered memory elements called flip-flops.  Master-Slave Flip-Flops (Pulse Triggered Flip-Flops) Aside from latches, two categories of flip-flops. – Master-slave flip-flops (pulse-triggered flip-flops) – Edge-triggered flip-flops Latches have immediate output response (known as transparency) May be undesirable: – May be necessary to sense the current state of a flip- flop while allowing new state information to be entered.  Master-Slave SR Flip-Flop Two sections, each capable of storing a binary symbol. First section is referred to as the master and the second section as the slave. Information is entered into the master on one edge or level of a control signal and is transferred to the slave on the next edge or level of the control signal. Each section is a latch.  Master-Slave SR Flip-Flop C = 0: – Master is disabled. Any changes to S,R ignored. – Slave is enabled. Is in the same state as the master. C = 1: – Slave is disabled (retains state of master) – Master is enabled, responds to inputs. Changes in state of master are not reflected in disabled slave. C = 0: – Master is disabled. – Slave is enabled and takes on new state of the master. Important: For short periods during rising and falling edges, both master and slave are disabled.  Master-Slave SR Flip-Flop Slave only takes on state Pulse of the master at 𝑡4. symbol indicates master Postponed output enabled indicator: output when C = 1 change postponed until and state of end of pulse master transferred If S, R = 1 when control to slave at signal goes from high to the end of low we are in an the pulse unpredicable state. Can period. cause metastable state.  Timing Diagram for Master-Slave SR flip-flop Master-Slave D Flip-Flop SENSE Sequential Circuits 50  Master-Slave JK Flip-Flop The output state of a master-slave SR flip-flop is undefined upon returning the control input to 0 when S = R = 1. – Necessary to avoid this condition. Master-slave JK flip-flop allows its two information input lines to be simultaneously 1. – Results in toggling the output of the flip flop.  Master-Slave JK Flip-Flop Assume in 1-state, C = 0, J = K = 1. – Due to feedback, the output of the J-gate is 0, output of K-gate is 1. – If clock is changed to C = 1 then master is reset. Assume in 0-state, C = 0, J = K = 1. – Due to feedback, the output of the J-gate is 1, output of K-gate is 0. – If clock is changed to C = 1 then master is set. 1 on J input line, 0 on K input line sets the flip-flop. – If in 1-state, unchanged b/c S,R set to 0. – If in 0-state, S set to 1, R set to 0. 0 on J input, 1 on K input line resets the flip-flop. Why? Master-Slave JK Flip-Flop  Timing Diagram for Master-Slave JK Flip-Flop  0’s and 1’s Catching The master is enabled during the entire period the control-signal is 1. If the slave latch is in its 1-state, then a logic-1 on K-input line causes the master-latch to reset. Slave becomes reset when control signal returns to 0. This is known as 0’s catching (2nd pulse). – Note: if a subsequent 1-signal on J input line and C is still 1, master does not become set again (due to feedback not changing). If slave latch is in 0-state, logic-1 on J input line while control signal is 1 causes the master latch to be set and slave will be set upon occurrence of the falling edge. This is known as 1’s catching (3rd pulse). In many applications, 0’s and 1’s catching behavior is undesirable. Normally recommended that the J and K input values should be held fixed during the entire interval the master is enabled. Any changes in J, K must occur while the control signal is 0.  0’s Catching Assume in 1-state 𝑄 = 1, 𝑄 = 0 , C = 1, J = 0, K = 0 𝐾 gets set to 1 briefly. – Master gets reset, Slave will become reset when Clock goes to 0. 𝐾 goes to 0. 𝐽 goes to 1. What happens? Nothing! Slave will still become reset when Clock goes to 0. Why?  Problems of Master-Slave F/F Master-slave flip-flops are also referred as pulse triggered flip-flops May cause errors when the delay of combinational feedback path is too long To solve: Ensure the delay of combinational block is short enough Use edge-triggered flip-flops instead SENSE Sequential Circuits 57  Edge-Triggered Flip-Flops In basic master-slave flip-flops, master is enabled during the entire period the control input is 1. – This can result in 0’s and 1’s catching. – To avoid this, signals on information lines are restricted from changing during the time the master is enabled. – Also a delay in the output since master’s state is established during the positive edge and transferred to the slave on the negative edge of clock. Edge-triggered flip-flops use just one of the edges of the clock signal. – This is referred to as the triggering edge. Response to triggering edge at the output of the flip-flop is almost immediate (depends only on propagation delay times). Once triggering occurs, flip-flop is unresponsive to information input changes until the next triggering edge.  Positive-Edge-Triggered D F/F If only SR latches are available, three latches are required Two latches are used for locking the two inputs (CLK & D) The final latch provides the output of the flipflop SENSE Sequential Circuits 59 Edge-Triggered D Flip-Flop 1. C = 0. Regardless of input at D, outputs of gates 2,3 are 1. So 𝑆 = 𝑅 = 1. State of latch is held. 2. Assume D = 0: Output of gate 4 is 1, output of gate 1 is 0. When C goes to 1: all inputs to gate 3 are 1, output changes to 0. Output of gate 2 remains at 1 since output of gate 1 is 0. So 𝑆 = 1, 𝑅 = 0. Output of gate 3 (0) is fed to input of gate 4. Output of gate 4, gate 1 not affected by changes to D. 3. Assume C = 0, D = 1. Outputs of gates 2,3, are 1. Output of gate 4 is 𝑆 𝑅 Latch 0, output of gate 1 is 1. When C goes to 1: output of gate 2 is 0, output of gate 3 remains at 1. So 𝑆 = 0, 𝑅 = 1. Output from gate 2 is input to gates 1, 3 so their outputs remain at 1. Changes in D have no affect on state of flip-flop while C = 1. Positive Edge-Triggered D Flip-Flop  Timing Diagram During setup and hold times 𝑡𝑠𝑢 , 𝑡ℎ with respect to the triggering edge of the clock, D input must not change.  Negative-Edge Triggered D Flip-Flop A falling edge (high to low transition) of control signal is used to sample the D input line. Simply place inverter at the control input of the flip-flop.  Edge-Triggered J-K Flip-Flop Logic diagram Characteristic Table Karnaugh map and characteristic equation: IC 7476 (J-K flip-flop) Datasheet The J-K flip-flop is versatile and widely used. The J and K designations for the inputs have no known significance except that they are adjacent letters in the alphabet. The function of the J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET, and no-change operation conditions. The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop. The input mark J is for set, and the input mark K is for reset. When both inputs J and K are equal to 1, the flip flop switches to its complement state; that is, if Q = 1, it switches to Q = 0 and vice versa. A J-K flip-flop is constructed with two crossed coupled NOR gates and two AND gates. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed with J and CP inputs, so the flip is set with a clock pulse only when Q' was previously 1. When both J and K are 1, the input pulse is transmitted through one AND gate only, the one whose input is connected to the flip-flop output presently equal to 1. Thus if Q = 1, the output of the upper AND gate becomes 1 upon application of the clock pulse and the flip-flop is cleared. If Q' = 1, the output of the lower AND gate becomes 1, and the flip-flop is set. In either case the output of the flip-flop is complemented. It is very important to realize that because of the feedback connection in the JK flip-flop, a CP pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing untill the pulse goes back to 0. To avoid this udesirable operation, the clock pulse must have a time duration that is shorter than the propegation delay time of the flip-flop. Another way to describe a JK flip-flop. Here, we describe the flip-flop by using the characteristic table rather than the characteristic equation. Positive-Edge-Triggered JK F/F SENSE Sequential Circuits 68 Positive-Edge Triggered T-Flip-Flop  Characteristic Equations Next state table: Shows the value of the next state of the flip-flop for each combination of values to the present state of the flip-flops and their information lines. The algebraic description of the next-state table of a flip-flop is called the characteristic equation of the flip-flop. Obtained by constructing the K-map for 𝑄+ in terms of the present state and information input variables. Next State Tables Characteristic Equations Excitation Table of J K F/F Excitation table - shows the minimum inputs that are required to generate a particular next state or to "excite" it to the next state, when the current state is known. They are similar to truth tables, except for the rearrangement of the data. Here, the current state and next state are next to each other on the left-hand side of the table, and the inputs needed to make that state change happen are shown on the right side of the table. 73 Excitation Table of T F/F 74  Flip – flop Conversions ▪ Generally, JK ffs and D ffs are the most widely used ffs. And so their availability in the form of IC’s is abundant. Numerous varieties of JK ff and D ff are available in the semiconductor market. The less popular SR ff and T ff are not available in the market as IC’s (even though a very few number of SR ffs are available as IC’s, they are not frequently used). ▪ There might be a situation where the less popular flip – flops are required in order to implement a logic circuit. In order use the less popular flip – flops, we will convert one type of flip – flop into another. Some of the most common flip – flop conversions are ▪ In order to convert one flip – flop to other type of flip – flop, we should design a combinational circuit(comb-ckt) that is connected to the actual flip – flop. Inputs to comb- ckt are same as the inputs of the desired ff. Outputs of comb-ckt are same as the inputs of the available ff. So the output of comb-ckt is connected to the input of our available flip – flop. ▪ SR ff to JK ff ▪ SR ff to D ff ▪ SR ff to T ff ▪ JK ff to SR ff ▪ JK ff to D ff ▪ JK ff to T ff ▪ D ff to SR ff ▪ D ff to JK ff SR Flip – flop to JK Flip – flop conversion Let’s write a truth table for the two inputs, J and K. For two inputs along with the QP, we get 8 possible combinations in truth table. Consider that when the two inputs are applied, QP is the present state and QN is the next state. For every combination of J, K ,QP , we find the corresponding QN state. Here QN will give the state values that to which the output of the JK flip – flop will jump after the present state, on applying the inputs. Now we write all the combinations of S and R in the truth table to get each QN value from corresponding QP. Hence these are the values of S and R that are used to change the state of flip flop from QP to QN. Conversion Table The K – map for S S = JQ’P.  The K – map for R R = KQP. The Boolean equations of S and R in terms of J, K and QP are: S = JQ’P and R = KQP  Steps for Conversion of flip-flops: Conversion of flip-flops causes one type of flip-flop to behave like another type of flip-flop. In order to make one flip-flop mimic the behavior of another certain additional circuitry and/or connections become necessary. Step 1: Write the Truth Table of the Desired Flip-Flop Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flip-flop to obtain a definite next state (Qn+1) from the known current state (Qn). Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop Step 5: Design the Necessary Circuit and make the Connections accordingly  SR Flip – flop to D Flip – flop Conversion table=Desired FF truth table + Given FF excitation table K – map to derive the Boolean eqn logic diagram of implementation of D Boolean eqn of S in of R in terms flip – flop from SR flip – flop terms of D of D S=D R = D’ The expression for the D input is The expression for the D input is  Registers Two basic ways in which information can be entered/outputted – Parallel: All 0/1 symbols handled simultaneously. Require as many lines as symbols being transferred. – Serial: Involves the symbol-by-symbol availability of information in a time sequence. Four possible ways registers can transfer information: – Serial-in/serial-out – Serial-in/parallel-out – Parallel-in/parallel-out – Parallel-in/serial-out Introduction: Registers ▪ An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information. ▪ The flip-flops store the information while the gates control when and how new information is transferred into the register. ▪ Some functions of register: ❖ retrieve data from register ❖ store/load new data into register (serial or parallel) ❖ shift the data within register (left or right) Introduction: Registers 83 Simple Registers ▪ No external gates. ▪ Example: A 4-bit register. A new 4-bit data is loaded every clock cycle. A3 A2 A1 A0 Q Q Q Q D D D D CP I3 I2 I1 I0 Simple Registers 84 Simple Registers ▪ No external gates. ▪ Example: A 4-bit register. A new 4-bit data is loaded every clock cycle. Simple Registers 85 Registers With Parallel Load ▪ Instead of loading the register at every clock pulse, we may want to control when to load. ▪ Loading a register: transfer new information into the register. Requires a load control input. ▪ Parallel loading: all bits are loaded simultaneously. Registers With Parallel Load 86 Registers With Parallel Load Load'.A0 + Load. I0 Load D Q A0 I0 D Q A1 I1 D Q A2 I2 D Q A3 I3 CLK CLEAR Registers With Parallel Load 87 Using Registers to implement Sequential Circuits ▪ A sequential circuit may consist of a register (memory) and a combinational circuit. Next-state value Register Combin- Clock ational circuit Inputs Outputs ▪ The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. ▪ The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices. Using Registers to implement 88 Sequential Circuits Shift Registers ▪ Another function of a register, besides storage, is to provide for data movements. ▪ Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses. Shift Registers 91  ▪ The short oversimplified answer is that it sees the data that was present at D prior to the clock. ▪ That is what is transferred to Q at clock time t1. The correct waveform is QC. At t1 Q goes to a zero if it is not already zero. The D register does not see a one until time t2, at which time Q goes high. Shift Registers ▪ Basic data movement in shift registers (four bits are used for illustration). Data in Data out Data out Data in (a) Serial in/shift right/serial out (b) Serial in/shift left/serial out Data in Data in Data in Data out Data out (c) Parallel in/serial out (d) Serial in/parallel out Data out (e) Parallel in / parallel out (f) Rotate right (g) Rotate left Shift Registers 93 Serial In/Serial Out Shift Registers ▪ Accepts data serially – one bit at a time – and also produces output serially. Serial data Q0 Q1 Q2 Q3 Serial data D Q D Q D Q D Q input output C C C C CLK Serial In/Serial Out Shift Registers 94 Serial In/Serial Out Shift Registers ▪ Application: Serial transfer of data from one register to another. SI SO SI SO Shift register A Shift register B Clock CP Shift control Clock Shift Wordtime control CP T1 T2 T3 T4 Serial transfer from register A to register B 95 Serial In/Serial Out Shift Registers ▪ Serial-transfer example. Timing Pulse Shift register A Shift register B Serial output of B Initial value 1 0 1 1 0 0 1 0 0 After T1 1 1 0 1 1 0 0 1 1 After T2 1 1 1 0 1 1 0 0 0 After T3 0 1 1 1 0 1 1 0 0 After T4 1 0 1 1 1 0 1 1 1 CS1104-13 Serial In/Serial Out Shift Registers 96  TESTBENCH VERILOG CODE FOR SISO AND TESTBENCH SISO module sisot_b; reg clk; module reg clear; sisomod(clk,clear,si,so); reg si; input clk,si,clear; wire so; sisomod uut output so; (.clk(clk),.clear(clear),.si(si),.so(so)); reg so; initial begin reg [3:0] tmp; clk = 0; clear = 0; always @(posedge clk ) si = 0; begin #5 clear=1’b1; if (clear) #5 clear=1’b0; #10 si=1’b1; tmp