Chapter 1: VLSI Design Methodology PDF

Chapter: 1 Introduction on VLSI Design Methodology 1. Overview of VLSI design methodology The structural complexity of digital integrated circuits (usually expressed by the number of transistors per chip) has been increasing at an exponential rate over the last thirty years. This phenomenal growth r...

Chapter: 1 Introduction on VLSI Design Methodology 1. Overview of VLSI design methodology The structural complexity of digital integrated circuits (usually expressed by the number of transistors per chip) has been increasing at an exponential rate over the last thirty years. This phenomenal growth rate has been sustained primarily by the constant advances in manufacturing technology, as well as by the increasing need for integrating more complex functions on chip. Answering the demands of the rapidly rising chip complexity has created significant challenges in many areas; practically hundreds of team members are involved in the development of a typical VLSI product, including the development of technology, computer-aided design (CAD) tools, chip design, fabrication, packaging, testing and reliability qualification. The efficient organization of these efforts under a well-structured system design methodology is essential for the development of economically viable VLSI products, in a timely manner. In this chapter, we will examine the overall flow of the design activities, important design concepts, various VLSI design styles, quality of design, and the CAD technology. Generally speaking, logic chips such as microprocessor chips and digital signal processing (DSP) chips contain not only large arrays of memory (SRAM/DRAM) cells, but also many different functional units. As a result, their design complexity is considered much higher than that of memory chips, although advanced memory chips also contain some sophisticated logic functions. Notice that the design complexity of logic increases almost exponentially with the number of transistors to be integrated. This is translated into an increase in the design cycle time, which is the time period from the start of chip development until the mask-tape delivery time. The majority of this design cycle time is typically devoted to achieving the desired level of chip performance at an acceptable cost, which is essential for the economical success of any competitive commercial product. During the course of the design cycle the circuit performance can usually be increased by design improvements; more rapidly in the beginning, then more gradually until the performance finally saturates for the particular design style and technology being used. The level of circuit performance which can be reached within a certain design time strongly depends on the efficiency of the design methodologies, as well as on the design style. This point is illustrated qualitatively in Fig. 1.1, where two different VLSI design styles are compared for their relative merits in the design of the same product. Using the full-custom design style (where the geometry and the placement of every transistor can be optimized individually) requires a longer time until design maturity can be reached, yet the inherent flexibility of adjusting almost every aspect of circuit design allows far more opportunity for circuit performance improvement during the design cycle. The final product typically has a high level of performance (e.g. high processing speed, low power dissipation) and the silicon area is relatively small because of better area utilization. But this comes at a larger cost in terms of design time. In contrast, using a semi-custom design style (such as standard-cell based design or FPGA) will allow a shorter design time until design maturity can be achieved. In the early design phase, the circuit performance can be even higher than that of a full-custom design, since some of the components used in semi-custom design are already optimized. But the semi-custom design style offers less opportunity for performance improvement over the long run, and the overall performance of the final product will inevitably be less than that of a full-custom design.\[1\] The choice of the particular design style for a VLSI product depends on the performance requirements, the technology being used, the expected lifetime of the product and the cost of the project. In the following sections, we will discuss the various aspects of different VLSI design styles and consider their impact upon circuit performance and overall cost. In addition to the proper choice of a VLSI design style, there are other issues which must be addressed in view of the constantly evolving nature of the VLSI manufacturing technologies. Approximately every two years, a new generation of technology is introduced, which typically allows for smaller device dimensions and consequently, higher integration density and higher performance. In order to make the best use of the current technology, the chip development time has to be short enough to allow the maturing of chip manufacturing and timely delivery of the product to customers. This may require that the level of logic integration and chip performance fall short of the level achievable with the current processing technology, as illustrated in Fig. 1.2. \[1\]. It can be seen that the design cycle time of a successful VLSI product is kept shorter than what would be necessary for developing an optimum-performance chip, thus leaving enough time for the production and marketing of the chip during the current generation, or \"technology window\". When the next generation of manufacturing technology arrives, the design can be updated to take advantage of higher integration density and better performance. On the other hand, if the design time of a particular product is kept excessively long to achieve the highest possible performance for the current generation of technology, there is a danger of missing the next technology window. A longer design cycle time usually results in better overall performance, but this product must then remain in the market for a certain amount of time in order to recover the development costs. Thus, the advantages brought by the next generation of manufacturing technologies cannot be realized, and the product becomes less competitive. In reality, the design cycle of the next generation chips usually overlaps with the production cycle of the current generation chips, thereby assuring continuity. The use of sophisticated computer-aided design (CAD) tools and methodologies are also essential for reducing the design cycle time and for managing the increasing design complexity \[1\]. 14.2. VLSI Design Flow "The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then a revision of requirements and an impact analysis must be considered"\[1\]. The Y-chart (first introduced by D. Gajski) shown in Fig. 1.3 illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter \"Y.\" "The Y-chart consists of three domains of representation, namely (i) behavioral domain, (ii) structural domain, and (iii) geometrical layout domain. The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnects area and signal delays. The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement and routing program. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In the standard cell based design style, leaf cells are pre-designed (at the transistor level) and stored in a library for logic implementation, effectively eliminating the need for the transistor level design. Figure 1.4 provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design: behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined for a successful design. For instance, if a chip designer defines an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom-up) as early as possible" \[1\]. "In the following, we will examine design methodologies and structured approaches which have been developed over the years to deal with both complex hardware and software projects. Regardless of the actual size of the project, the basic principles of structured design will improve the prospects of success. Some of the classical techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality".\[1\] 1.3. Design Hierarchy "The use of the hierarchy, or \"divide and conquer\" technique involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. This approach is very similar to software development wherein large programs are split into smaller and smaller sections until simple subroutines, with well-defined functions and interfaces, can be written. In Section 1.2, we have seen that the design of a VLSI chip can be represented in three domains. Correspondingly, a hierarchy structure can be described in each domain separately. However, it is important for the simplicity of design that the hierarchies in different domains be mapped into each other easily"\[2\]. "In the physical domain, partitioning a complex system into its various functional blocks will provide a valuable guide for the actual realization of these blocks on the chip. Obviously, the approximate shape and size (area) of each sub-module should be estimated in order to provide a useful floorplan. Figure 1.6 shows the hierarchical decomposition of the four-bit adder in physical description (geometrical layout) domain, resulting in a simple floorplan. This physical view describes the external geometry of the adder, the locations of input and output pins, and the pin locations that allow some signals (in this case the carry signals) to be transferred from one sub-block to the other without external routing. At lower levels of the physical hierarchy, the internal mask layout of each adder cell defines the locations and the connections of each transistor and wire"\[1\]. Figure 1.7 shows the "full-custom layout of a 16-bit dynamic CMOS adder, and the sub modules that describe the lower levels of its physical hierarchy. Here, the 16-bit adder consists of a cascade connection of four 4-bit adders, and each 4-bit adder can again be decomposed into its functional blocks such as the Manchester chain, carry/propagate circuits and the output buffers. Finally, Fig. 1.8 shows the structural hierarchy of the 16 bit adder. Note that there is a corresponding physical description for every module in the structural hierarchy, i.e., the components of the physical view closely match this structural view".\[1\].1.4. Concepts of Regularity, Modularity and Locality "The hierarchical design approach reduces the design complexity by dividing the large system into several sub-modules. Usually, other design concepts and design approaches are also needed to simplify the process. Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. A good example of regularity is the design of array structures consisting of identical cells - such as a parallel multiplication array. Regularity can exist at all levels of abstraction. For example, at the transistor level, uniformly sized transistors simplify the design and at the logic level, identical gate structures can be used. Figure 1.9 shows regular circuit-level designs of a 2-1 MUX (multiplexer) and a D-type edge-triggered flip flop. Note that both of these circuits were designed by using inverters and tri-state buffers only. If the designer has a small library of well-characterized basic building blocks, a number of different functions can be constructed by using this principle. Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces. Modularity allows that each block or module can be designed relatively independently from each other, since there is no ambiguity about the function and the signal interface of these blocks. All of the blocks can be combined with ease at the end of the design process, to form the large system. The concept of modularity enables the parallelization of the design process. The well-defined functionality and signal interface also allow the use of generic modules in various designs. By defining well-characterized interfaces for each module in the system, we effectively ensure that the internals of each module become unimportant to the exterior modules. Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible. This last point is extremely important for avoiding long interconnect delays. Time-critical operations should be performed locally, without the need to access distant modules or signals. If necessary, the replication of some logic may solve this problem in large system architectures. Decomposition of the four-bit adder in physical description (geometrical layout) domain, resulting in a simple floorplan. This physical view describes the external geometry of the adder, the locations of input and output pins, and the pin locations that allow some signals (in this case the carry signals) to be transferred from one sub-block to the other without external routing. At lower levels of the physical hierarchy, the internal mask layout of each adder cell defines the locations and the connections of each transistor and wire. Figure 1.7 shows the full-custom layout of a 16-bit dynamic CMOS adder, and the sub modules that describe the lower levels of its physical hierarchy. Here, the 16-bit adder consists of a cascade connection of four 4-bit adders, and each 4-bit adder can again be decomposed into its functional blocks such as the Manchester chain, carry/propagate circuits and the output buffers.".\[1\] Finally, Fig. 1.8 shows the structural hierarchy of the 16 bit adder. Note that there is a corresponding physical description for every module in the structural hierarchy, i.e., the components of the physical view closely match this structural view. 1.5. VLSI Design Styles Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the specified functionality at low cost and in a timely manner, as explained in Section 1.1., Field Programmable Gate Array (FPGA): "Fully fabricated FPGA chips containing thousands or even more, of logic gates with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality. This design style provides a means for fast prototyping and also for cost-effective chip design, especially for low-volume applications. A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures. The programming of the interconnects is accomplished by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. Thus, the signal routing between the CLBs and the I/O blocks is accomplished by setting the configurable switch matrices accordingly. The general architecture of an FPGA chip from Xilinx is shown in Fig. 1.10. A more detailed view showing the locations of switch matrices used for interconnect routing is given in Fig. 1.11."\[1\] "The simplified block diagram of a CLB (XC4000 family from Xilinx) is shown in Fig. 1.12. In this example, each CLB contains two independent 4-input combinational function generators, a clock signal terminal, user-programmable multiplexers and two flip-flops. The function generators, which are capable of realizing any arbitrarily defined Boolean function of their four inputs, are implemented as memory look-up tables. A third function generator can implement any Boolean function of its three inputs: F, G\' and a third input from outside, the CLB. Thus, the CLB offers significant flexibility of implementing a wide range of functions, with up to nine input variables. The user programmable multiplexers within the CLB control the internal signal routing, and therefore, the functionality of the block. The complexity of a FPGA chip is typically determined by the number of CLBs it contains. In the Xilinx XC4000 family of FPGAs, the size of the CLB array can range from 8 x 8 (64 CLBs) to 32 x 32 (1024 CLBs), where the latter example has an approximate gate count of 25,000. Typical FPGA chips can support system clock frequencies between 50 and 100 MHz. With the use of dedicated computer-aided design tools, the gate utilization rate (percentage of gates on the FPGA which are actually used in a particular design) can exceed 90%. The typical design flow of an FPGA chip starts with the behavioral description of its functionality, using a hardware description language such as VHDL. The synthesized architecture is then technology-mapped (or partitioned) into circuits or logic cells. At this stage, the chip design is completely described in terms of available logic cells. Next, the placement and routing step assigns individual logic cells to FPGA sites (CLBs) and determines the routing patterns among the cells in accordance with the netlist. After routing is completed, the on-chip performance of the design can be simulated and verified before downloading the design for programming of the FPGA chip. The programming of the chip remains valid as long as the chip is powered-on, or until it is re-programmed. The largest advantage of FPGA-based design is the very short turn-around time, i.e., the time required from the start of the design process until a functional chip is available. Since no physical manufacturing step is necessary for customizing the FPGA chip, a functional sample can be obtained almost as soon as the design is mapped into a specific technology. The typical price of FPGA chips is usually higher than other alternatives (such as gate array or standard cells) of the same design, but for small volume production of ASIC chips and for fast prototyping, FPGA offers a very valuable option".\[1\] 1.6. Design Quality It is desirable to measure the quality of design in order to improve the chip design. Although no universally accepted metric exists to measure the design quality, the following criteria are\' considered to be important: ϖ Testability ϖ Yield and manufacturability ϖ Reliability ϖ Technology updateability Testability: "Developed chips are eventually inserted into printed circuit boards or multichip modules for system applications. The correct functionality of the system hinges upon the correct functionality of the chips used. Therefore, fabricated chips should be fully testable to ensure that all the chips passing the specified chip test can be inserted into the system, either in packaged or in bare die form, without causing failures. Such a goal requires ¬ Generation of good test vectors ¬ Availability of reliable test fixture at speed ¬ Design of testable chip In fact, some chip projects had to be abandoned after chip fabrication because of inadequate testability of the design. As the complexity of the chips increases with the increasing level of monolithic integration, additional circuitry has to be included to ensure that the fabricated chips can be fully tested. This translates into an increase in chip area and some speed penalty, but such a trade-off will become unavoidable in VLSI design"\[1\] Yield and Manufacturability: "If we assume that the test procedure is flawless, the chip yield can be calculated by dividing the number of good tested chips by the total number of tested chips. However, this calculation may not correctly reflect the quality of the design or the processing. The most strict definition of the yield can be the number of good tested chips divided by the total number of chip sites available at the start of the wafer processing. However, since some wafers may be scrapped in the process line due to mishandling or for other reasons, such a metric may not reflect the design quality. Also, poor design of the wafer array for chips may cause some chips to fail routinely due to uncontrollable process variations and handling problems. On the other hand, poor chip design can cause processing problems and, therefore, drop-outs during the processing. In such a case, the first yield metric will overestimate the design quality. The chip yield can be further divided into the following subcategories: ϖ Functional yield ϖ Parametric yield The functional yield is obtained by testing the functionality of the chip at a speed usually lower than the required chip speed. The functional test weeds out the problems of shorts, opens and leakage current, and can detect logic and circuit design faults. The parametric test is usually performed at the required speed on chips that passed the functional test. All the delay testing is performed at this stage. Poor design that failed to consider uncontrollable process variations which cause significant variations in chip performance may cause poor parametric yield, thus, significant manufacturing problems. In order to achieve high chip yield, chip designers should consider manufacturability of the chip by considering realistic fluctuations in device parameters that cause performance fluctuations".\[1\] Reliability: The reliability of the chip depends on the design and process conditions. The major causes for chip reliability problems can be characterized into the following: ¬ Electrostatic discharge (ESD) and electrical overstress (EOS) ¬ Electromigration ¬ Latch-up in CMOS I/O and internal circuits ¬ Hot-carrier induced aging ¬ Oxide breakdown ¬ Single event upset ¬ Power and ground bouncing ¬ On-chip noise and crosstalk "Usually the wafer lots with poor yields also cause reliability problems. For example, when a particular wafer processing is poorly controlled, thus causing aluminum overetching, many chips on the wafer may suffer from open-circuited metallic interconnects. Some chips with severely overetched, but not fully open-circuited interconnects, may pass the test. But, under current stress, such interconnects can be open-circuited because of electromigration problems, causing chip and system failures in the field. Any good manufacturing practice should weed out such potential failures during the accelerated reliability test. Nevertheless, for any specified process, chip design can be improved to overcome such process-dependent reliability problems. For example, knowing that aluminum over etching can occur, alert designers may choose to widen the metal width beyond the minimum width allowed. Similarly, to avoid the transistor aging problem due to hot carrier aging, designers can improve the circuit reliability with proper sizing of transistors or by reducing the rise time of signals feeding into the nMOS transistor gate. The protection of 10 circuits against electrostatic damages (ESD) and latch-up is another example".\[1\] Technology Updateability: "Process technology development has progressed rapidly and as a result, the lifespan of a given technology generation has remained almost constant even for submicron technologies. Yet, the time pressure to develop increasingly more complex chips in a shorter time is constantly increasing. Under such circumstances, the chip products often have to be technology-updated to new design rules. Even without any change in the chip\'s functionality, the task of updating the mask to new design rules is very formidable. The so-called \"dumb shrink\" method whereby mask dimensions are scaled uniformly, is rarely practiced due to non-ideal scaling of device feature sizes and technology parameters. Thus, the design style should be chosen such that the technology update of the chip or functional modules for design reuse can be achieved quickly with minimal cost. Designers can develop and use advanced CAD tools that can automatically generate the physical layout, the so-called silicon compilation, which meets the timing requirements with proper gate sizing or transistor sizing"\[1\]. 1.7. Packaging Technology "Novice designers often fail to give enough consideration to the packaging technology, especially in the early stages of chip development. However, many high-performance VLSI chip scan fail stringent test specifications after packaging if chip designers have not included various effects of packaging constraints and parasitic in their design. The numbers of ground planes and power planes and the bonding pads greatly affect the behaviors of the on-chip power and ground buses. Also the length of the bonding wire between the chip and the package and the lead length in the package determine the inductive voltage drop in the output circuit. An equally important consideration is thermal problems. Good packages should provide low thermal resistance and, hence, limited temperature increase beyond the ambient temperature due to power dissipation. Since the choice of proper packaging technology is critical to the success of the chip development, chip designers should work closely with package designers from the start of the project, especially for full custom designs. Also, since the final cost of the packaged chip depends largely on the package cost itself, for low-cost chip development, designers must ensure enough design margins that the chips can function properly in low-cost packages with more parasitic effects and less thermal conductivity. Some of the important packaging concerns are ¬ Hermetic seals to prevent the penetration of moisture ¬ Thermal conductivity ¬ Thermal expansion coefficient ¬ Pin density ¬ Parasitic inductance and capacitance ¬ a-particle protection Various types of packages are available for integrated circuit chips. Integrated circuit packages are generally classified by the method which is used to solder the package on the printed circuit board (PCB). The package pins can be introduced in holes drilled in the (PCB); this method is called pin-through-hole (PTH). Alternatively, the package pins can be directly soldered on the PCB; this method is called surface-mounted technology (SMT). PTH packages require that a precise hole be drilled in the PCB for each pin, which is not a cost-effective process. Moreover, holes usually require metal plating on their interior surface to ensure conductivity, and the lack of proper plating may cause yield and reliability problems. Nevertheless, PTH packages have the advantage that they can be soldered using a relatively inexpensive soldering process. In comparison, SMT packages are usually more cost- and space-effective, yet soldering of SMT packages on the PCB requires more expensive equipment. Plastic has been the dominating material for IC packages for many years, although it has the disadvantage of being permeable to environmental moisture. Ceramic packages are used when power dissipation, performance or environmental requirements justify the relatively higher cost".\[1\] Some common IC package types are: Dual In-line Packages (DIP): "This PTH package has been the most dominant IC package type for more than 20 years. DIP have the advantage of low cost but their dimensions can be prohibitive, especially for small, portable products. DIP are also characterized by their high interconnect inductances, which can lead to significant noise problems in high-frequency applications. The maximum pin count of DIP is typically limited to 64"\[1\]. Pin Grid Array (PGA) Packages: "This PTH package type offers a higher pin count (typically 100 to more than 400 pins) and higher thermal conductivity (hence, better power dissipation characteristics) compared to DIPs, especially when a passive or active heat sink is attached on the package. The PGA packages require a large PCB area, and the package cost is higher than DIP, especially for ceramic PGAs"\[1\]. Chip Carier Packages (CCP): "This SMT package type is available in two variations, the leadless chip carrier and the leaded chip carrier. The leadless chip carrier is designed to be mounted directly on the PCB, and it can support a high pin count. The main drawback is the inherent difference in thermal coefficients between the chip carrier and the PCB, which can eventually cause mechanical stresses to occur on the surface of the PCB. The leaded chip carrier package solves this problem since the added leads can accomodate small dimension variations caused by the differences in thermal coefficients"\[1\]. Quad Flat Packs (QFP): "This SMT package type is similar to leaded chip carrier packages, except that the leads extend outward rather than being bent under the package body. Ceramic and plastic QFPs with very high pin counts (up to 500) are becoming popular package types in recent years"\[1\]. Multi-Chip Modules (MCM): This IC package option can be used for special applications requiring very high performance, where multiple chips are assembled on a common substrate contained in a single package. Thus, a large number of critical interconnections between the chips can be made within the package. Advantages include significant savings of overall system size, reduced package lead counts and faster operation since chips can be placed in very close proximity.