415_hw5.pdf

11 , 19. 441704/26 King Saud University Semester II, 1445 H College of Computer and Information Sciences...

11 , 19. 441704/26 King Saud University Semester II, 1445 H College of Computer and Information Sciences CEN 415, VLSI Design Computer Engineering Department 3 Credits Homework 2 Homework number 5 (DUE 12/5/2024) Question 1 a) What is the activity factor at each node, if the inputs have activity P = 0.5 b) Find the minimal test sequence to test for stuck at faults for the previous circuit. Question 2 For the circuit shown below assume that the times in the following table: Max Min Thold, Tsetup 1 0.5 Clk-Q 1 0.5 Max td 10 ns Max td 7 ns FF FF Min td 3 ns Min td 2 ns   a) What is the minimum cycle time? b) What is the maximum skew the circuit can tolerate, if the cycle time is 15ns? Question 3 a) In the system of two flip-flops shown below what is the minimum clock cycle time with no skew between clocks? Assume the setup time of the flop is 0.3ns, the clk-to-q delay is 0.2ns and the hold time is 0.4ns. So essentially the D-Q delay of the flop is 0.5ns, assuming that the data arrives before the clock. The dotted line and the values in the logic block indicate the maximum logic delay between input and output. Highlight the critical path. 1 b) The clocks can be skewed from each other by 1.5ns. This means that the clock to flop1 can arrive 1.5ns earlier than the clock to flop2 (skew type1) or the clock to flop2 can arrive 1.5ns earlier than the clock to flop1 (skew type2). Also assume that the skew amount and direction are time invariant, i.e. either type1 or type2 can occur in a system, not both. Recalculate the minimum cycle time of part (a) and indicate which one of the two types of skew described above causes the worst case skew. c) The minimum cycle time with latch based system is hard to determine, since in a latch based system you can borrow time from your neighboring phase as long as the logic in that phase does not need all its time. The circuit below is almost the same circuit only the flop is replaced by a phi2- phi1 flip- flop. Assume that the D-Q delay through each latch is 0.25ns (there is no setup time, hold time and clk-to-q delay in this system).Draw the critical path and find out the minimum cycle time of this system. d) Recalculate the minimum cycle time of part (c) with the skew conditions similar to part (b). Also indicate the worst case skew type. Question 4 In this problem will look at some timing constraints in a 2 phase clocked system. For this problem assume that the latches are perfect – Td-q, Tc-q, Thold, Tsetup are all 0 and assume that there is 1ns of clock skew. CL CL Latch Latch Max td 10ns Max td 8ns Min td 2 ns Min td 1 ns Phi1 Phi2 a) What is the minimum time Cycle time? b) What is the minimum non-overlap between 1 and 2? (This number can be positive and negative) c) What is the maximum time borrowing possible? 2 Question 5 2 -- (3 points) Given the following gate. 𝑓 = 𝑎𝑏 + 𝑐 Draw a high skewed version of the gate, and size the inputs. What is the logical effort for each input? Question 6 (3 points) Draw the domino gate for the following function 𝑓 = 𝑎𝑏 + 𝑐𝑑 Question 7 ̅̅̅ use bubble pushing to (3 points) Given both the inputs and their complements and the function. 𝑓 = 𝑎𝑏 + 𝑐(𝑒𝑔) produce this function with inversion only in the inputs. 3  ~ = May 17 0 0 S =. 1875. &3 & = +. 25 0. n ef 029 d. S ruy = 0. 29 SAI SAR V2 9 10113201003 & I & I UI 201003 310113 · ↳ my 201d3 (10113 us (10113201003 minimal set = [10113 201003 LoloB. , & Tc = typ + Apcp + Esceap => 10 + 1 + 1312n) DT = 19nS Tc = typ + +pen + tap + +sker + Skers 1-10-1-153mS so the maximum skew time is us & T = Sns + 0. 3 + 0. 273 5n).  & To post +Psa - > cons + 8nS -18ns D Ins < 2 + thenever lap ↓ on overlap 3- 1 as tonover lap & so its & & Turner = T - ( - - ( + 1) 48 ns  - Op- · lig & · 26 + 1) · ~ · I I ↓ 6 & C E fu In = - Mi = - Ij on = 8= Hi s & f = = + ( + j) = n( Cy + in - P -- i