VLSI Notes PDF

# Bhavena Mam ## Design MOD-6 Counter **Problem:** Design a MOD-6 counter and write a program in VHDL for it. **Solution:** To design a MOD-6 counter, we need to use a MOD-8 counter circuit with some modifications. We can use the following formulas: - **MOD number** = $2^n - 1$, where *n* is...

# Bhavena Mam ## Design MOD-6 Counter **Problem:** Design a MOD-6 counter and write a program in VHDL for it. **Solution:** To design a MOD-6 counter, we need to use a MOD-8 counter circuit with some modifications. We can use the following formulas: - **MOD number** = $2^n - 1$, where *n* is the number of bits. - **Count number** = $2^n - 1 = 2^3 - 1 = 7$ (for MOD-8) For a MOD-6 counter, we need a 6-state count. Therefore, the count number will be 6 - 1 = 5. ### MOD-8 Truth Table | QC | QB | QA | Count | |---|---|---|---| | 0 | 0 | 0 | (0) | | 0 | 0 | 1 | (1) | | 0 | 1 | 0 | (2) | | 0 | 1 | 1 | (3) | | 1 | 0 | 0 | (4) | | 1 | 0 | 1 | (5) | | 1 | 1 | 0 | (6) - Reset Number | | 1 | 1 | 1 | (7) | ### Logic Circuit The logic circuit is a MOD-8 counter with a reset logic to create a MOD-6 counter. When the count reaches 6, the reset logic is activated, and the count resets to 0. ### VHDL Code ```VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Source is port( Clk, rst: in STD_LOGIC; Count: inout STD_LOGIC_VECTOR(3 downto 0) ); end source; architecture Behavioral of source is begin process(clk, rst) begin if (rst = '1') then Count <= "0000"; elsif (falling_edge(clk)) then Count <= Count + 1; if (Count = "110") then Count <= "0000"; elsif (falling_edge(clk)) then Count <= Count + 1; end if; end if; end process; end behavioral; ``` # Explain Johnson Counter **Problem:** Explain Johnson counter and write a VHDL program for it. **Solution:** Johnson counter, also known as a modified ring counter, is designed with a group of flip-flops where the inverted output from the last flip-flop is connected to the input of the first flip-flop. It can be implemented using D flip-flops or JK flip-flops. It's also known as an inverted feedback counter or twisted ring counter. This type of counter follows a specific sequence of bit patterns, using only half the number of flip-flops compared to the ring counter. Thus, the MOD will be 2n, where n is the number of flip-flops. ### Johnson Counter Circuit Diagram The circuit diagram shows a Johnson counter with four flip-flops. ### VHDL Code ```VHDL Library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Johnsoncounter is port( clk : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end Johnsoncounter; architecture Behavioral of Johnsoncounter is signal tmp : STD_LOGIC_VECTOR(3 downto 0) := "0000"; begin process(clk, rst) begin if (rst = '1') then tmp <= "0000"; elsif (rising_edge(clk)) then tmp(1) <= tmp(0); tmp(2) <= tmp(1); tmp(3) <= tmp(2); tmp(0) <= tmp(3); end if; end process; Q <= tmp; end Behavioral; ``` # Inertial Delay Model vs. Transport Delay Model **Problem:** Write a note on inertial delay model and transport delay model. **Solution:** Delay is a mechanism to make something happen at a later time than originally planned or expected. There are two types of delay models used with signal assignments: inertial delay model and transport delay model. ## Inertial Delay Model An inertial delay model represents the delays often found in switching circuits. It models the time for which an input value must be stable before the value is allowed to propagate to the output. If the input is not stable for the specified time, no output change occurs. When used with signal assignments, the input value is represented by the value of the expression, and the output is represented by the target signal. For example, if the delay is 10ns, and the input signal changes at 5ns and 8ns, those values are not stable for the 10ns delay and will not propagate to the output. The signal will only propagate to the output if the signal is stable for more than 10ns. This type of delay is commonly found in digital circuits and is often used to filter out unwanted spikes and transients on signals. ## Transport Delay Model A transport delay model models the delay in hardware that does not exhibit any inertial delay. This delay represents pure propagation delay - any change on the input is transported to the output, no matter how short the change is, after the specified delay. For example, if the delay is 10ns, and the input signal changes at 5ns, 8ns, 12ns, the output will change at 15ns, 18ns, 22ns respectively. This type of delay model is used when there is a need for fast and accurate propagation of signals, such as in high-speed circuits. # Structural Model for Logic Expression **Problem:** Write a structural model for the following logic expression: ``` Y = ABCDE + A'B'C'E' + AB'C + AD'E' ``` **Solution:** ```VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SOP_FORM is port( A: in STD_LOGIC; B: in STD_LOGIC; C: in STD_LOGIC; D: in STD_LOGIC; E: in STD_LOGIC; Y: out STD_LOGIC ); end SOP_FORM; architecture Behavioral of SOP_FORM is component ANDGATE5 is port( A, B, C, D, E: in STD_LOGIC; Y: out STD_LOGIC ); end component; component ANDGATE4 is port( A, B, C, D: in STD_LOGIC; Y: out STD_LOGIC ); end component; component ANDGATE3 is port( A, B, C: in STD_LOGIC; Y: out STD_LOGIC ); end component; component NOTGATE is port( A: in STD_LOGIC; Y: out STD_LOGIC ); end component; component ORGATE is port( A, B, C, D: in STD_LOGIC; Y: out STD_LOGIC ); end component; signal n1, n2, n3, n4, n5, n6, n7, n8, n9: STD_LOGIC; begin X18: NOTGATE port map (A, n1); X19: NOTGATE port map (B, n2); X20: NOTGATE port map (C, n3); X21: NOTGATE port map (D, n4); X22: NOTGATE port map (E, n5); X6: ANDGATE5 port map (A, B, C, D, E, n6); X7: ANDGATE4 port map (n1, n2, n3, n5, n7); X8: ANDGATE3 port map (A, n2, n3, n8); X9: ANDGATE3 port map (n1, n4, n5, n9); X10: ORGATE port map (n6, n7, n8, n9, Y); end Behavioral; ``` # Scalar and Composite Data Types in VHDL **Problem:** Define data types used in VHDL. Explain scalar and composite types in detail with examples. **Solution:** In VHDL, a data object can hold a value that belongs to a set of values. This set of values is specified using a type declaration. A type is a name that has a set of values and operations associated with it. There are two main categories of data types in VHDL: scalar types and composite types. ## Scalar Data Types Scalar types are ordered and have relational operators. The values belonging to scalar types can be compared using relational operators. There are four different kinds of scalar data types in VHDL: 1. **Enumeration Types:** - These types define a set of user-defined values, which are usually identifiers or character literals. - For example: ```VHDL type color is ('Red', 'Orange', 'Yellow'); type alphabet is ('A', 'B', 'C'); ``` 2. **Integer Types:** - These types define a range of integer values. - For example: ```VHDL type INDEX is range 31 downto 0; type My_word is range 4 to 6; ``` 3. **Physical Types:** - These types are used to define measurements units for physical quantities like length, time, pressure, etc. - The range defines the minimum and maximum values of the quantity. - For example: ```VHDL type capacity is range 0 to 105 units nf: nano Farad; MF: micro Farad; mf: mili Farad; F: Farad; end units; ``` 4. **Floating Point Types:** - These types define a range of real numbers. - For example: ```VHDL type TTL_VOLTAGE is range -5.5 to -104; type REAL_DATA is range 0.00 to 31.9; ``` ## Composite Data Types Composite data types represent collections of values. There are two main types of composite data types: 1. **Array Types:** - These types define a collection of values that are all of the same type. - For example: ```VHDL type t_vector is array(0 to 12) of integer; variable SUM: INTEGER range 0 to 100 := 1; ``` 2. **Record Types:** - These types define a collection of values that can be of different types. - For example: ```VHDL type student is record name: string(1 to 10); roll_no: integer; marks: array(1 to 5) of integer; end record; ``` # entity buffer and inout **Problem:** Differentiate between entity port mode `buffer` and `inout`. **Solution:** In VHDL, the `buffer` and `inout` ports are used to allow bidirectional data flow between an entity and its environment. However, there are some key differences between the two port modes: - **`buffer` port:** - A `buffer` port can only have one source of data, but multiple destinations can read from it. - The data written to a `buffer` port is immediately reflected to the input port of the entity. - It is suitable for situations where data is only being updated by a single source, such as when a component is storing data that may be read by other parts of the design. - **`inout` port:** - An `inout` port can have multiple sources and multiple destinations. - The data on an `inout` port is not immediately reflected to the entity’s input port. Instead, the updated value is stored in the entity’s internal storage until the next time the port is updated, or until the entity’s internal storage is updated. - It is suitable for situations where data is being exchanged between multiple components, such as when a component is interacting with a shared memory location. The choice of which port mode to use depends on the specific requirements of your design. If you need bidirectional data flow with a single source, use a `buffer` port. If you need bidirectional data flow with multiple sources, use an `inout` port. # Additional Notes - The notes are written by a student and may contain errors or inaccuracies. - The student is taking a course on VHDL and digital logic. - The student is learning about different types of counters, delay models, and data types in VHDL. - The student is also trying to apply their knowledge to solve problems related to VHDL programming. - The student is improving their understanding of VHDL and digital logic through these notes.