ARM Cortex M0+ Processor Intro
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What is the primary advantage of the ARM Cortex-M0+ processor's Von Neumann architecture?

  • Enhanced security through isolated memory spaces.
  • Increased processing speed due to parallel data and instruction access.
  • Reduced power consumption due to separate buses.
  • Simplified memory management for both program and data. (correct)

Which feature of the ARM Cortex-M0+ processor is MOST directly related to minimizing power consumption?

  • Thumb instruction set architecture
  • Wait for Interrupt (WFI) mode (correct)
  • JTAG/SWD Debug Interface
  • Nested Vector Interrupt Controller (NVIC)

How does the Thumb instruction set architecture contribute to the ARM Cortex-M0+'s efficiency?

  • By increasing code density with mostly 16-bit instructions. (correct)
  • By enabling dynamic instruction scheduling for optimized performance.
  • By allowing direct execution of legacy ARM code.
  • By primarily using 32-bit instructions for complex operations.

A developer needs to prioritize interrupt handling in an ARM Cortex-M0+ based system. Which feature allows them to configure interrupt priorities?

<p>Nested Vector Interrupt Controller (NVIC) (C)</p> Signup and view all the answers

What is the role of the 'Fetch + pre-decode' stage in the ARM Cortex-M0+ processor's pipeline?

<p>Retrieving the instruction from memory and performing initial processing. (D)</p> Signup and view all the answers

In the context of a microcontroller (MCU), which component is responsible for performing arithmetic and logical operations?

<p>Microprocessor (MPU) (A)</p> Signup and view all the answers

Which of the following best describes the role of the Wake-up Interrupt Controller (WIC) in the ARM Cortex-M0+ processor?

<p>Enabling the processor to exit low-power modes in response to an interrupt. (D)</p> Signup and view all the answers

What is the key architectural difference between a Microprocessor (MPU) and a Microcontroller (MCU)?

<p>MCUs integrate the MPU core with memory and peripherals on a single chip. (A)</p> Signup and view all the answers

What is a key characteristic that licensees must adhere to when using the ARM architecture?

<p>They must follow the ARM CPU architecture and instruction set. (C)</p> Signup and view all the answers

Why might an assembly language program designed for peripherals on one ARM chip not function correctly on another ARM chip?

<p>Functional registers and their physical locations for peripherals are not standardized. (D)</p> Signup and view all the answers

What are the two main approaches for programming peripherals on an ARM chip?

<p>Using a propriety device library from the ARM chip vendor or writing customized programs. (B)</p> Signup and view all the answers

Given the ARM assembly code snippet:

CMP R0, #9 BLE label_LE ADD R1, R0, #55 B next label_LE ADD R1, R0, #48 next …

If R0 initially holds the value 5, what value will R1 hold after executing this code?

<p>53 (D)</p> Signup and view all the answers

An engineer needs to display the letter 'C' on a screen using its ASCII code. Based on the information provided, which numerical representation (in decimal) should the engineer use?

<p>67 (D)</p> Signup and view all the answers

What is the primary trade-off between RISC and CISC architectures?

<p>RISC has a larger code size but less complicated hardware, while CISC has shorter code length but more complex hardware. (D)</p> Signup and view all the answers

Which of the following is a key characteristic of RISC (Reduced Instruction Set Computer) architecture?

<p>Simplified instruction set where each instruction typically executes in one clock cycle. (A)</p> Signup and view all the answers

Which developers were recognized for their work on RISC architecture?

<p>David Patterson, John Hennessy, Stephen Furber and Sophie Wilson. (A)</p> Signup and view all the answers

David Jagger's work with ARM included the invention of which key architectural feature?

<p>The Thumb architecture for improved code density. (A)</p> Signup and view all the answers

What are the sizes of FLASH and SRAM in STM32C071x8/xB MCUs?

<p>FLASH: 128 KB, SRAM: 36 KB (D)</p> Signup and view all the answers

Which bus architecture provides better back-to-back access performance in STM32C071x8/xB MCUs?

<p>The AHB (Advanced High-Performance Bus). (A)</p> Signup and view all the answers

The ARM Cortex-M0+ instruction set is characterized by?

<p>A limited set of instructions, including both 16-bit and 32-bit instructions, suitable for control applications. (B)</p> Signup and view all the answers

What does 'ADD R0, R1, R2' do in assembly language?

<p>It adds the values in registers R1 and R2, storing the result in R0. (C)</p> Signup and view all the answers

What does the 'S' suffix indicate in some ARM Cortex-M0+ instructions?

<p>The instruction will update the status flags (Negative, Zero, Carry, Overflow). (B)</p> Signup and view all the answers

In the context of the provided material, what is the purpose of an optocoupler in a typical application scenario?

<p>To isolate and detect signals in electrically noisy environments. (D)</p> Signup and view all the answers

Flashcards

Microcontroller (MCU)

Microcontroller = Microprocessor + Memory + Peripherals.

Microcomputer

A microcontroller on a single silicon chip.

Von Neumann Structure

Pathway/bus competition in Von Neumann architecture.

ARM Cortex-M0+ Processor

32-bit MPU architecture introduced in 2012.

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Two-Stage Pipeline

Fetch + pre-decode, decode + execute.

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Thumb Instruction Set Architecture (ISA)

Most instructions are 16-bit.

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Nested Vector Interrupt Controller (NVIC)

Interrupt prioritization and masking.

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ARM

Advanced RISC Machine; uses RISC principles.

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CMP R0, #9; BLE label_LE

Compares R0 to 9, if R0 <= 9, jumps to label_LE, otherwise adds 55 to R0 and stores result in R1, then jumps to next. At label_LE adds 48 to R0 and stores result in R1.

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ASCII

A numerical representation of characters.

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ASCII Codes for '0'–'9'

Numbers '0' through '9' are represented by ASCII codes 48 through 57.

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ASCII Codes for 'A'–'F'

Letters 'A' through 'F' are represented by ASCII codes 65 through 70.

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ARM Licensing

Licensees must follow ARM CPU architecture and instruction set, but can implement custom peripherals. Functional registers and their physical locations are not standardized.

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RISC

Reduced Instruction Set Computer. Each instruction performs one operation in one clock cycle.

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CISC

Complex Instruction Set Computer. One instruction can perform multiple operations over several clock cycles.

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AHB (Advanced High-Performance Bus)

High-performance bus, allows for better back-to-back access performance.

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APB (Advanced Peripheral Bus)

Legacy bus for connecting peripherals.

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CPU

Central Processing Unit. Executes program instructions.

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LED

Light Emitting Diode. A semiconductor light source for signalling purposes.

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Piezo Buzzer

Audio signaling device used to provide feedback, like a click or beep.

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Optocoupler

Combines a light emitter and receiver, used for signal detection in noisy electrical environments.

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BEQ label

Used to branch to a specific label/address if the previous operation resulted in an equal status or zero flag.

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ADD R0, R1, R2

Adds the values in registers R1 and R2, and stores the result in register R0, without altering flags.

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Study Notes

  • Introduction to the ARM Cortex M0+ Processor.

Where the study notes are going

  • ARM Cortex-M0+ processor information
  • STM32C071x8/xB MCUs
  • ARM Cortex-M0+ instruction set

Microcontroller (MCU)

  • A microcontroller consists of a microprocessor (MPU), memory, and peripherals
  • A microcomputer is a microcontroller on a single silicon chip
  • 99% of microcomputers are microcontrollers on a single silicon chip

ARM Cortex-M0+ Processor (1)

  • A 32-bit MPU
  • Introduced in 2012
  • ARMv6-M architecture
  • Uses a two-stage pipeline, with fetch, pre-decode, decode, and execute stages
  • Thumb instruction set architecture (ISA)
  • Most instructions are 16-bit
  • It has a Von Neumann structure with a shared pathway/bus for programs and data, leading to pathway/bus competition

ARM Cortex-M0+ Processor (2)

  • Has a built-in interrupt controller
  • Features a nested vector interrupt controller (NVIC)
  • Employs interrupt prioritization and masking
  • Offers 4 programmable priority levels + NMI (Non-Maskable Interrupt)
  • The low-power support is 9.8 uW/MHz (90 nm semiconductor process)
  • Has sleep and deep sleep modes
  • Features Wait for Input (WFI)/Wait for Event (WFE)
  • Includes a Wake-up Interrupt Controller (WIC)
  • Uses Debug: JTAG/SWD

ARM and RISC

  • ARM: Advanced RISC Machine
  • First developed by Acorn Computers in the mid-80s
  • Developed based on the RISC (Reduced Instruction Set Computing) concept by Stanford & Berkeley
  • A separate company licenses ARM cores to STMicroelectronics, Texas Instruments, Atmel, and Motorola
  • RISC: Reduced Instruction Set Computer: One instruction for one operation, executed within one clock cycle, larger code size but less complicated hardware that is advantageous
  • CISC: Complex Instruction Set Computer: One instruction for multiple operations, run over several clock cycles, shorter code lengths but complex with (control) hardware

Pioneers in RISC Computers

  • 2022 Charles Stark Draper Prize for Engineering
  • Conceptualization, prototyping, and benchmarking in the 1980s
  • David Patterson, UC Berkeley
  • John Hennessy, Stanford
  • Commercialization
  • Stephen Furber and Sophie Wilson, Acorn Computers
  • Acorn/Advanced RISC machine (ARM)

UC Inventor of RISC Embedded Processors

  • David Jagger
  • B.S. from UC, Computer Science in 1987
  • M.S. from UC, Computer Science in 1991
  • Computer Scientist at ARM, 1992-2000
  • Designer of ARM7, ARM10
  • Thesis title: A performance study of the Acorn RISC machine
  • Inventor of the Thumb architecture
  • Received the James Clerk Maxwell Medal from IEEE, 2019

STM32C071x8/xB MCU Architecture

  • FLASH: 128 KB
  • SRAM: 36 KB
  • AHB: Advanced High-Performance Bus with better back-to-back access performance.
  • APB: Advanced Peripheral Bus: Legacy bus
  • RCC: RESET & Clock Control
  • CRC: Cyclic Redundancy Check
  • EXTI: Extended Interrupt & Event Controller

System Overview: STM32C071x8/xB MCUs

  • Based on ARM Cortex-M0+ CPU
  • STM32C071RBT6
  • STM32C071CB
  • STM32C071KB
  • Has modules relevant to the course
  • STM32C071GBU6

Typical Application Scenario

  • Program: contains code and data
  • Central Processing Unit (CPU): ARM Cortex-M0+ processor
  • LED: Lights Emitting Diode
  • Semiconductor light source used for signalling
  • Piezo buzzer
  • Audio signalling device to indicate button pressing (click, ring, or beep)

Cortex-M0+ Instructions

  • 56 are 16-bit instructions
  • 6 are 32-bit instructions
  • Not suitable for heavy-duty number-crunching tasks.
  • S: Causes an instruction to update flags - Negative, Zero, Carry, overflow
  • Rd: result register
  • Rn/Rm: First/second source register
  • cc: conditional execution (EQ, NE, GT, LT, LE, …)

Example Program in Assembly

  • BEQ label: Branch to label if previous operation results in equal status (Z = 1)
  • ADD R0, R1, R2: Carry out R0 = R1 + R2 without affecting the flags

Supplementary Materials

  • Fundamental data types
  • ASCII table
  • ARM licensing
  • Evolution of ARM process architecture

Fundamental Data Types

  • Type Class, Machine Type, Bytes size, Byte alignment, Note

ASCII Table

  • American Standard Code for Information Interchange
  • Numerical representation of characters
  • Code 48 – 57 represents '0' – '9'
  • Code 65 – 70 represents 'A' – 'F'
  • Hex numerical system has 16 symbols

ARM Licensing (1)

  • The Licensee must follow the ARM CPU architecture and instruction set
  • Functional registers and their physical locations are not standardized
  • Has the freedom to implement its own peripherals (I/O ports, ADCs, Timers, SPI…)
  • Assembly language programs for any ARM chip can be run on any ARM chip
  • Assembly language programs for peripherals on one ARM chip may not be able to run on other ARM chips

ARM Licensing (2)

  • Developed by ARM bus Matrix
  • Developed by ARM or Chip Manufacturers
  • Memory, I/Os

Evolution of ARM Processor Architecture

  • Has different versions of ARM processor architecture and their evolution.

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Introduction to ARM Cortex M0+ Processor PDF

Description

Study notes covering the ARM Cortex-M0+ processor, a 32-bit MPU introduced in 2012. Covers the ARMv6-M architecture, instruction set, and interrupt controller. Also discusses the STM32C071x8/xB MCUs.

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