CSA-102 Digital Electronics Past Paper June 2023 PDF

Total Printed Pages: 02 Roll No. :……………... CSA-102 Examination –June- 2023...

Total Printed Pages: 02 Roll No. :……………... CSA-102 Examination –June- 2023 B.Tech. I Sem : CSA- 102 - Digital Electronics Time : 2 Hrs Max. Marks : 60 Min. Marks : 19 Note: Total number of questions are 05. All Questions are compulsory. Each Question has 4 parts (a, b, c, d). Part a & b are compulsory while Part c & d has internal Choice. Assume missing data, if any. Word limit be observed as follows: Part a & b – Objective type/Fill in the blanks/One sentence answer. Part c – Max 100 words and Part d – Max 400 words. Word limit NOT to be followed for diagram, numerical, derivation. BL CO PO PI Code Q.1 (a) (i) Representation of 5 in 2 4 2 1 code is ……………….. 02 (ii) The 1’s complements of 101101101 is ………… (b) (i) The humming code are used for ……………………. 02 (ii) The gray code of (101101)2 is …………………………… (c) Perform the BCD addition (575)10 + (258)10 03 OR Convert (562)8 to (N)16 03 (d) Solve the following : 05 (a) Convert (01AB)16 to (N)2 (b) (154)10 to (N)8 (c) Subtract (011011)2 – (110011)2 (d) (21.54)8 to (N)10 (e) 2’s complement of (1011010)2 OR A 7-bit Hamming code 1011110 is received in which almost 05 a single error has occurred. Locate the position of the error bit using parity checks assuming code was created using an odd parity Q.2 (a) (i) When any one of the input is high the output is high gate 02 is now as ……….. (ii) The logical sum of two or more logical product terms is called……………………. (b) Two advantages of K-Map over Boolean theorem 02 1  (c) Draw all logical gates using NANAD gate 03 OR SOP of F= ∑(0,1,2,4,6) is …………………….. 03 (d) Find SOP for F = ∑ (1,3,7,11,15) + d ( 0,2,5) 05 OR Find POS F = π (0,1,2,3,4,10,11) 05 Q.3 (a) (i) How much input and output needed for demultiplexer….. 02 (ii) How many select lines would be required for an 8-line- to-1-line multiplexer………….. (b) How many 16 x 1 multiplexer required building 32 x 1 02 multiplexer, draw it. (c) Implement the Boolean expression F(A,B,C) = ∑ m (0,1,3,6) 03 using 4:1 multiplexer. OR Construct a 5ꓫ32 decoder using four 3ꓫ8 decoder and one 03 2ꓫ4 decoder (d) Implement a full adder. 05 OR Implement full substractor using decoder. 05 Q.4 (a) (i) Which flip flop is commonly used to implement the 02 registers……….. (ii) If an active-HIGH S-R Flip Flop has a 0 on the S input and a 1 on the R input then the output is …….. (b) Draw the truth table of T Flip Flop 02 (c) Convert JK Flip Flop to T Flip Flop. 03 OR What is the difference between Sequential Circuit and 03 combinational circuit? (d) Explain the working of JK flip Flop with characteristics and 05 2  Excitation table OR Explain different type of shift register explain them with 05 neat diagram. Q.5 (a) (i) In the toggle mode, a JK flip-flop has the input 02 ……………. (ii) How many types of the counter are there……….. (b) (i) In asynchronous counter the clock pulse should be 02 ………….for each flip flop. (ii) A decimal counter has ……… states. (c) Write a difference between Asynchronous and Synchronous 03 counter OR Design 2-bit asynchronous up counter using J-K flip-flop 03 (d) Design a 3-bit Synchronous up counter using T flip-flop 05 OR Design a 3 bit counter that count up to 5. 05 ***** 3