Understanding Direct Memory Access (DMA)

Direct Memory Access (DMA)

• Enables peripheral devices to directly manage the memory bus.
• Improves data transfer speed between peripherals and memory.
• Achieves this without constant CPU intervention.

Need for DMA

• Peripheral devices manage the memory bus directly.
• Increases the speed of data transfer between a peripheral device and memory.
• Decreases intervention from the CPU.

CPU Bus Signals for DMA

• Two control signals are used to facilitate DMA transfer: BUS REQUEST and BUS GRANT.
• BUS REQUEST: A signal from the DMA controller to the CPU.
• The DMA controller requests the CPU relinquish control of the buses.
• If the input is high, the CPU ceases instruction execution.
• The address, data, read, and write lines are set to high impedance.
• BUS GRANT: A signal from the CPU to the DMA controller.
• Shows that the CPU to DMA controller to the buses are in a high impedance state.
• DMA assumes control of buses, which allows memory transfers to occur without the CPU.
• Once the transfer is done, the bus request line and bus grant signal are disabled and the CPU resumes normal operation.

DMA Transfer Modes

• There are two main modes: Burst Transfer and Cycle Stealing.
• Burst Transfer: A block of multiple words is continuously transferred.
• DMA controller becomes the master of the memory buses.
• High-speed peripheral devices, magnetic disks use/take advantage of it.
• Cycle Stealing: Transfers a single data word at a time.
• Control of the buses returns to the CPU after each word transfer.
• The CPU delays its operation for one memory cycle.

DMA Controller

• DMA is similar to an interface and serves as a communication channel between the CPU and I/O devices.
• Communication with the CPU is established through data and control lines.
• I/O device communication uses a DMA request and Acknowledge.
• When BG = 0, the CPU communicates with the DMA register via the data bus for reading or writing.
• When BG = 1, the CPU relinquishes the buses, allowing DMA to perform memory operations.
• DMA specifies the memory address in the address bus and enabling read/write signals.
• Components: address register, word count register, and control register.
• Address Register: Stores the memory address for data transfer and increments after each transfer.
• Word Count Register: Holds the number of words to be transferred, decrements after transfer, and tests for zero.
• Control Register which will specify the mode of transfer.

DMA Initialization

• The CPU initializes DMA by executing I/O instructions, which include the address to choose DMA registers.
• The CPU sends the starting memory address for read/write operations.
• It also transmits the word count (the number of words in the memory block).
• Lastly, the mode of data transfer (read/write) and a signal to start DMA transfer are sent from the CPU.
• After DMA is initialized, the CPU stops communicating with DMA, and DMA begins transferring data between memory and the peripheral.

DMA Operation

• Each DMA has its independent address, activating the DS and RS lines.
• The CPU initializes the DMA through the data bus.
• A peripheral device sends a DMA request, the DMA controller activates the BR line to inform the CPU,
• The CPU allows this by enabling the BG line.
• DMA transfers the value of the address register to the address bus and enables DMA Acknowledge.
• The peripheral device transfers the data (write) or receives the data (read) via the data bus.
• The DMA updates the address and word count registers for each transfer.
• Should the word count not reach zero, DMA continues to check the request line from the peripheral device.
• The DMA disables the BR line to the CPU when peripheral speed slows and the CPU continues its program.
• When the word count reaches zero, DMA stops the transfer and disables the BR line to the CPU.

Additional DMA Features

• DMA controller can have multiple channels
• Each has a request and acknowledge pair for separate devices.
• Each channel has its own address and word count register.
• Priority is assigned among channels.
• Higher-priority channels are serviced first.

DMA Applications

• Fast data transfer between magnetic disks and memory.
• Updating the display on an interactive terminal.

Example Calculation: I/O Data Transfer Rate with DMA

• Computer with a CPU and an I/O device connected to main memory.
• Shared bus with a 16-bit data bus width.
• The CPU:
• Executes 10^6 instructions per second.
• Requires 5 processor cycles per instruction.
• Reads or writes uses 1 processor cycle.
• Background programs occupy 95% of the instruction rate.
• One processor cycle is equal to one bus cycle.
• DMA module uses all available cycles.
• Ignores setup/status-checking time.
• CPU Utilization:
• Busy 95% of the time.
• Leaves 5% for non-instruction tasks.
• DMA During CPU Activity: Uses 0.95 x 3 cycles.
• DMA During CPU Idle Time: Uses 0.05 x 6 cycles.
• Total DMA Cycles:
• (0.05 x 6 + 0.95 x 3) cycles.
• Calculation:
• Rate of Transfer = 1,000,000 x (0.05 x 6 + 0.95 x 3) = 3.15 x 10^6 words per second1.

Hard disk with DMA data transfer to Memory running at 300MHZ

• Takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively.
• The transfer size is 20 Kbytes.
• Total Transfer Time = (Total Data) / (Total Transfer Rate)
• Total Transfer rate=20 MB per second = 20 × 2²⁰ bytes/sec
• Total Data=20 KB=20 × 2¹⁰ bytes
• Processor Time = (Cycles for DMA transfer) / (Processor Speed)
• CPU requires 300+900=1200 cycles
• Time=1200 cycles/(300 × 10⁶) cycles/sec = 4 ×10 ⁻⁶ sec = .004 ms
• % Processor Time = (Processor Time/Total Time ) × 100

Hard disk with DMA data transfer to Memory running at 600MHZ

• Total Transfer rate=10 MB per second = 10 × 2²⁰ bytes/sec
• Total Data=20 KB=20 × 2¹⁰ bytes
• Processor Time = (Cycles for DMA transfer) / (Processor Speed)
• CPU requires 300+900=1200 cycles
• Time=1200 cycles/(600 × 10⁶) cycles/sec = 2 ×10 ⁻⁶ sec = .002 ms
• % Processor Time = (Processor Time/Total Time ) × 100