CPS 310 Lecture 6: Direct Memory Access

• CPS 310 Lecture 6 is about Direct Memory Access (DMA), I/O peripherals and multiprocessing, taught by Professor Alex Ufkes
• Required purchases include the ELEGOO UNO Project Super Starter Kit and the Arduino UNO-3 with Atmega328P microcontroller; a course outline is on Amazon

ARCTools I/O Ports

• The console data port is at memory address 0xffff0000.
• The console status port is at memory address 0xffff0004.
• The keyboard data port is at memory address 0xffff0008.
• The keyboard status port is at memory address 0xffff000C.

Read & Print all the Characters

• A code snippet manages input, reads a keystroke, and executes a conditional branch based on the input
• The input waiting loop remains the same.
• After reading a keystroke, the code subtracts 27 from register %r31
• 27 is the ASCII code for the Escape key
• If the result is zero, it branches to the end of the program
• An output waiting loop is also present.
• The program branches back to iwait to repeat the process unless the Escape key is pressed, which branches to end.

Busy-Waiting and Interrupts

• Busy-waiting is inefficient because the CPU polls I/O devices, wasting time while waiting for input.
• Interrupts are an alternative where the keyboard signals the processor when a character is ready, avoiding constant polling.
• The keyboard raises an interrupt to signal readiness
• Handling interrupts involves updating the fetch-execute cycle to check for interrupts and initiate an interrupt handler.
• This introduces overhead that is tiny compared to the cost of programmed I/O
• Different interrupts trigger different handlers called Interrupt Service Routines (ISRs).
• One ISR might be for the keyboard, another for a hard disk, and another for a system timer.
• ISRs are subroutines commonly provided by the operating system.

Direct Memory Access (DMA)

• DMA is performed by a separate module on the system bus.
• DMA transfers data to or from main memory, initiated by the CPU sending a command to the DMA module.
• The command specifies the I/O device address, read/write operation, memory address, and number of words to transfer.
• Once data transfer completes, the DMA module issues an interrupt.
• The DMA module exists as part of the system bus, not typically of the CPU.
• During DMA transfer, the processor is free to perform other tasks.
• DMA transfers an entire block of data directly to and from memory, bypassing the processor.
• The processor is only involved at the beginning and end of the transfer.
• After finishing its transfer, the DMA module sends an interrupt to the processor.
• There is a potential drawback where the processor might execute more slowly if it needs to access the system bus during a DMA transfer.
• This is because the CPU would have to wait one bus cycle
• Cycle-Stealing DMA is a technique where the DMA module holds the bus for one word transfer, then relinquishes it and requests bus control for each subsequent word.
• This prevents DMA from tying up the bus and interfering with other operations
• Cycle-stealing DMA helps balance bus access

CPU Cycle vs Bus Cycle

• In practice, DMA has minimal impact on CPU performance because bus speeds typically range from 66 to 800 MHz.
• It does not saturate the bus because I/O devices are slow
• The CPU doesn't need the bus when fetching from cache.

Common I/O Interfaces

• Memory mapped I/O schemes simplify I/O device utilization.
• The system’s communication intricacies with these devices are hidden.
• The fact that loading and storing at an I/O mapped address is easy doesn’t mean implementing that mapping is simple too.
• Every I/O device has unique idiosyncrasies and protocols.
• Standardized protocols are common among I/O devices.
• The common I/O devices, SATA, USB, PCI, PCIe, VGA, DVI, and HDMI use standard protocols.

System Bus Architecture

• The ARC system bus is 32 bits wide.
• The data bus is 32-bit which enables one to load a full word in a single instruction cycle and facilitates parallel bit transmission
• The address bus is also 32-bit, with each instruction being 32 bits in length which placed in parallel on the address bus.
• Serial bus architectures contrast with the parallel system bus.
• Parallel ports are a common feature on older systems, especially for printers, and transferred data in parallel

Serial Bus Architecture

• Serial communication offers advantages over parallel, it is more economical at shorter distances.
• Serial interfaces require higher bit-rates to compensate for the lack of parallelism and offer physical/economic benefits with thinner cables using less space
• Serial consumes less power due to fewer data pins and simplifies timing management.
• Parallel interconnects are generally used inside the computer, while serial interconnects are used outside.

Common I/O Interfaces (cont)

• Recommended Standard-232 (RS-232) was common before USB for low-bit-rate devices like mice and keyboards, and is still used in embedded systems and industrial applications
• A RXD pin receives data and a TXD pin sends it and these pins are crossed to allow simultaneous sending and receiving of data.
• The Universal Serial Bus (USB) replaced RS-232 in modern PC systems.
• USB has many flavors and connectors, such as Mini-USB, USB Type-B and A, and USB-C.
• USB-C is reversible
• USB devices are plug-and-play and define a common communication standard for peripherals.
• USB evolved from USB 2.0 to USB 3.0, offering 12 Mbps, 480 Mbps, and 5 Gbps, respectively; USB 3.2 with USB-C connectors can reach up to 20 Gbps
• USB devices are managed by a host controller and data is transferred from a USB device through a host controller managed with drivers into a program.
• The extensible Host Controller Interface (xHCI) is a computer interface specification for a USB host controller, typically part of a motherboard's chipset and handles power distribution, communication, and other tasks.
• The operating system uses device drivers to communicate with the HCI.
• A system call is used to get data into our program in a high-level language.
• By scanning and calling, in assembly, can specific system subroutines.

Keyboard Functionality

• In modern systems, the OS maintains software buffers for I/O devices and supplies keystrokes from these buffers.
• Keyboards have internal buffers and older models could only handle a limited number of simultaneous key presses.
• Modern keyboards allow to push as many buttons into notepad and their will each be reported

Keyboards In Depth

• The QWERTY layout was designed to be deliberately inefficient to prevent physical jamming of mechanical mechanisms.
• ECMA-23 standard uses 7 bits per character for transmission but is insufficient for modifier keys.
• Modern keyboards use an internal processor called a microcontroller.
• Keypresses close circuits in the key matrix, where each key indicates one character based on an onboard character map, and then the state of key matrix is transmitted
• The keyboard's microcontroller analyzes the state of the key matrix.
• This state is translated into a character, characters are placed into onboard buffer and sent via USB using the according protocol.
• The HCI receives keyboard data which means that the Operating System then talks to HCI passing to the application which interprets as content or the keystrokes are simply ignored

Serial ATA (SATA)

• SATA interfaces can connect HDDs, SSDs, or optical drives whereas M.2 SSDs can come in other formats.
• Parallel ATA (PATA) preceded Serial ATA (SATA)
• SATA’s cables can have a thinner profile and take up less space.
• SATA devices are hot-swappable, allow for add/remove of SATA devices without needing to power down the system, the functionality requires OS support however.
• Windows 95/98 do not support SATA devices as the OS's predate their development
• AHCI (Advanced Host Controller Interface) is a common theme in storage.
• AHCI is a storage interface, devices implement existing standards liek USB or SATA.
• Mass storage devices use SATA, USB, or NVMe (for SSDs).
• The AHCI works commonly through motherboard's chipset but can also pass through PCIe cards or from a chip on Motherboard
• South bridges and North bridges manage connections on the motherboard.
• Bridges are chips on the motherboard that manage and connect the various buses.
• The North bridge is no longer used with functions incorporated into the CPU.
• South bridges and North bridges work with chipset which need to work with the CPU

PCI Express

• Peripheral Component Interconnect Express (PCIe) is typically used for connecting Graphics Processing Units (GPUs).
• GPUs drive multiple displays and perform parallel graphics rendering
• PCI components sound and network interface cards(NICs).
• Nowadays, these parts are integrated into the chipset or motherboard
• The GPUs has many cores and is used for highly parallelized operations and are less useful for general computing.

Multiprocessing

• Multiprocessing, or parallel processing, was developed because program's speed is limited by the fetch-execute cycle.
• This can improve with pipelining, which starts the next instruction before the current one finishes.
• Higher clock frequencies generate more heat.
• Amdahl's Law discusses the limits of the performance with a parallel design
• Speedup= (time to execute on single processor) / (time to execute on p parallel processors) = 1/( f + (1-f)/p) where f is the time of sequential code and p is number of processors
• Even with small values of ƒ are added, eventually diminishing the value of parallel design
• Realistically, performance peaks at 4-6 cores
• Software engineers are working to apply parallel processing to data management, reducing code needing serial processing.
• Modern GPUs have thousands of cores, used for tasks like computer vision that is for operating in tandem performing simple operations of thousands of pixels to speed up image processing