Sequential Logic Circuits: Design and Types

• Module 5 covers the design of sequential logic circuits

Sequential Circuits

• Consist of a combinational circuit connected to storage elements, forming a feedback path.
• Storage elements store binary information.
• The binary data in these elements defines the sequential circuit's state at a given time.
• Outputs depend on both current inputs and the present state of storage elements.
• Sequential Circuit is made up of Combinational logic and Memory elements.

Asynchronous vs Synchronous Sequential Circuits

• Asynchronous Sequential Circuits, the inputs go to a combinational circuit and memory elements which provides outputs
• Synchronous Sequential Circuits, the inputs go to a combinational circuit which has a clock input going to flip-flops, and this provides outputs

Introduction to Sequential Circuits

• Two types of sequential circuits are synchronous and asynchronous.
• Synchronous circuits: outputs only change at specific times.
• Asynchronous circuits: outputs may change at any time.
• A multivibrator is a class of sequential circuits.
• Three subtypes of multivibrators are bistable (2 stable states), monostable (one-shot with 1 stable state), and astable (no stable state).
• Bistable logic devices: latches and flip-flops.
• Latches and flip-flops change state using different methods.

Memory Elements

• Memory elements remembers a value indefinitely or can change its value when commanded from inputs
• Basic memory element has command inputs (Set, Reset) and outputs Q and Q' (stored value).

Characteristic Table of a Memory Element

• Set: Q(t+1) = 1
• Reset: Q(t+1) = 0
• Memorize: Q(t+1) = 0
• No Change: Q(t+1) = 1
• Q(t): Current state / Present State (PS)
• Q(t+1): Next State (NS) or Q+

Memory Elements with Clock

• Flip-flops are memory elements with a clock signal that change on clock singals
• Clock is usually a square wave
• Positive edges are rising edges
• Negative edges are falling edges

Triggering/Activation

• Two types of triggering/activation, being Pulse(level)-triggered and Edge-triggered

Pulse/Level-Triggered

• Latches utilize Pulse/Level-Triggering
• ON = 1, OFF = 0

Edge-Triggered

• Flip-flops utilize Edge-Triggering
• Positive edge-triggered: ON = from 0 to 1; OFF = other time
• Negative edge-triggered: ON = from 1 to 0; OFF = other time

S-R Latch

• When output Q is high, SR Latch is in SET state.
• When output Q is low, SR Latch is in RESET state.
• SR Latch has two outputs: Q and Q'.

Active-High Input S-R Latch

• Also known as a NOR gate latch
• R=HIGH (and S=LOW) results in RESET state.
• S=HIGH (and R=LOW) results in SET state.
• Both inputs LOW results in no change.
• Both inputs HIGH results in an invalid state where Q and Q' are both LOW.

Active-LOW Input S'-R' Latch

• Also known as NAND gate latch
• R'=LOW (and S'=HIGH) results in RESET state.
• S'=LOW (and R'=HIGH) results in SET state.
• Both inputs HIGH results in no change.
• Both inputs LOW results in an invalid condition.
• Drawback: Invalid condition exists and must be avoided.

Characteristics Table for Active-High Input S-R Latch:

• S=0, R=0: No change, Latch remains in present state.
• S=1, R=0: Latch SET, Q = 1, Q' = 0.
• S=0, R=1: Latch RESET, Q = 0, Q' = 1.
• S=1, R=1: Invalid condition, Q = 0, Q' = 0.

Characteristics Table for Active-Low Input S'-R' Latch:

• S’=1, R’=1: No change, Latch remains in present state
• S’=0, R’=1: Latch SET, Q = 1, Q’ = 0
• S’=1, R’=0: Latch RESET, Q = 0, Q’ = 1
• S’=0, R’=0: Invalid condition, Q = 1, Q’ = 1

SR Latch values

• S R Q0 (Initial Q) Q Q’
• 0 0 0 0 1 Q = Q0
• 0 0 1 1 0
• 0 1 0 0 1 Q=0
• 0 1 1 0 1
• 1 0 0 1 0 Q=1
• 1 0 1 1 0
• 1 1 0 x x Q=x
• 1 1 1 x x Q=x

Controlled (Gated) Latches

• Control input enables or disables the latch.

SR Latch with Control Input Table

• C S R Q
• 0 x x Q0 No change
• 1 0 0 Q0 No change
• 1 0 1 0 Reset
• 1 1 0 1 Set
• 1 1 1 Q=Q’ Invalid

D Latch (D = Data) Timing Diagram

• Control input (C) determines when data (D) is latched.

Table of D Latch

• C D Q
• 0 x Q0 No change
• 1 0 0 Reset
• 1 1 1 Set
• Output may change when C is active.

Latch Circuits

• Latches are not suitable for Synchronous logic circuits
• The enable signal gates excitation inputs directly to the output Q, causing immediate changes.
• Solution: Using a clock signal to restrict the times the states of memory elements change
• Edge-triggered memory elements (flip-flops) are a result of this problem

Edge-Triggered Flip-Flops

• Edge-triggered flip-flops are known as synchronous bistable devices
• Outputs change state on a specific triggering input called the clock.
• State changes occur either at the positive (rising), or negative (falling) edge of the clock signal.

Edge-Triggered Flip-Flops

• S-R, D, and J-K edge-triggered flip-flops utilize a ">" symbol at the clock input.
• There are variations of positive and negative edge-triggered flipflops for the types S-R, D, and J-K

S-R Flip-Flop

• On the triggering edge of the clock pulse.
• S=HIGH (and R=LOW) results in SET state.
• R=HIGH (and S=LOW) results in RESET state.
• Both inputs LOW results in no change
• Both inputs HIGH is an invalid condition

Characteristic Table of a Positive Edge-Triggered S-R Flip-Flop:

• S=0, R=0: No change, Q(t+1) = Q(t)

• S=0, R=1: Reset, Q(t+1) = 0

• S=1, R=0: Set, Q(t+1) = 1

• S=1, R=1: Invalid

• X = irrelevant

• ↑ = clock transition LOW to HIGH

D Flip-Flop

• Single input D (data).
• D=HIGH results in SET state.
• D=LOW results in RESET state.
• Q follows D at the clock edge.
• A D flip-flop can be created by converting an S-R flip-flop with an inverter.

Table of D Flip-Flop

• D CLK Q(t+1) Comments
• 1 ↑ 1 Set
• 0 ↑ 0 Reset
• ↑ = clock transition LOW to HIGH

J-K Flip-Flop

• Q and Q' are fed back to the pulse-steering NAND/AND gates
• No invalid state occurs
• Includes a Toggle State
• J=HIGH (and K=LOW) results in a SET state.
• K=HIGH (and J=LOW) results in a RESET state.
• Both inputs LOW results in no change
• Both inputs HIGH results in Toggle

Characteristic Table

• J K CLK Q(t+1) Comments
• 0 0 ↑ Q(t) No change
• 0 1 ↑ 0 Reset
• 1 0 ↑ 1 Set
• 1 1 ↑ Q(t)’ Toggle

Excitation Table

• Q(t) Q(t+1) J K
• 0 0 0 X
• 0 1 1 X
• 1 0 X 1
• 1 1 X 0

T Flip-Flop

• The T flip flop is a single-input version of the J-K flip flop
• It is formed by tying both inputs together

Characteristic Table

• T CLK Q(t+1) Comments
• 0 ↑ Q(t) No change
• 1 ↑ Q(t)’ Toggle

Excitation Table

• Q(t) Q(t+1) T
• 0 0 0
• 0 1 1
• 1 0 1
• 1 1 0

Flip-Flop Characteristic Tables Overview

• S-R Flip-Flop:
• S R Q(t+1)
• 0 0 Q(t) No change
• 0 1 0 Reset
• 1 0 1 Set
• 1 1 X Invalid
• D Flip-Flop:
• D Q(t+1)
• 0 0 Reset
• 1 1 Set
• JK Flip-Flop:
• J K Q(t+1)
• 0 0 Q(t) No change
• 0 1 0 Reset
• 1 0 1 Set
• 1 1 Q’(t) Toggle
• T Flip-Flop:
• T Q(t+1)
• 0 Q(t) No change
• 1 Q’(t) Toggle

Flip-Flop Excitation Table Overview

• S-R Flip-Flop:
• Q(t) Q(t+1) S R
• 0 0 0 X
• 0 1 1 0
• 1 0 0 1
• 1 1 X 0
• D Flip-Flop:
• Q(t) Q(t+1) D
• 0 0 0
• 0 1 1
• 1 0 0
• 1 1 1
• JK Flip-Flop:
• Q(t) Q(t+1) J K
• 0 0 0 X
• 0 1 1 X
• 1 0 X 1
• 1 1 X 0
• T Flip-Flop:
• Q(t) Q(t+1) T
• 0 0 0
• 0 1 1
• 1 0 1
• 1 1 0

Flip-Flop Characteristic Equations

• S-R Flip-Flop: Q(t+1) = S + R’Q
• D Flip-Flop: Q(t+1) = D
• JK Flip-Flop: Q(t+1) = JQ’ + K’Q
• T Flip-Flop: Q(t+1) = TQ’+T’Q