RTL Synthesis Overview

RTL Synthesis

• RTL synthesis is the initial stage in logic synthesis, translating Verilog code into a netlist of generic logic gates.
• RTL synthesis includes parsing and elaboration.
• Parsing reads RTL files and generates a data structure for subsequent processing.
• Elaboration ensures the connections among RTL-specified components are legitimate.

RTL Synthesis: Parsing

• Parsing involves lexical analysis, grammar/syntax checking and syntax tree building.
• Lexical analysis identifies keywords and identifiers.
• Grammar/syntax checking verifies the correctness of the Verilog code.
• A syntax tree is built if the grammar is correct, which is a hierarchical data structure representing the Verilog code.

RTL Synthesis: Elaboration

• Elaboration involves connecting components and ensuring their legitimacy.
• Legitimate connections are represented in the internal model.
• Errors are reported for illegitimate connections.
• Elaboration also handles parameterized modules.
• Parameterized modules are created with different interfaces for varying parameters.

RTL Synthesis: Verilog Constructs to Circuit

• Synthesizable Verilog constructs are translated into circuit elements.
• Non-synthesizable constructs are not translated into circuit elements.
• Non-synthesizable constructs are helpful for other design tasks, such as functional verification.
• Delay specification is a typically non-synthesizable construct.