Programmable Interfacing Devices: PPI 8255

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Questions and Answers

What is the total number of pins in the PPI 8255?

40 pins (correct)

64 pins

20 pins

32 pins

Which ports on the PPI 8255 can work in BSR mode?

PORT B and PORT C

Only PORT A

Only PORT C (correct)

All three ports (A, B, and C)

Which control group consists of port A and port C upper in the PPI 8255?

Control group A (correct)

I/O control group

Control group B

Data control group

What is the main function of the PPI 8255?

To interface the CPU with external devices Signup and view all the answers

In which mode do all three ports of PPI 8255 work as simple input or output functions without interrupt handling capabilities?

Mode 0 Signup and view all the answers

Which data pins are used for transferring data in the PPI 8255?

D0-D7 Signup and view all the answers

What is the function of the control register in PPI 8255?

To select input-output functions or BSR mode Signup and view all the answers

Which pins are responsible for selecting different ports in PPI 8255?

A1 and A0 Signup and view all the answers

What is the primary function of port C in the PPI 8255?

Handshake signaling Signup and view all the answers

In which mode does the PPI 8255 allow both port A and B to function simultaneously as input or output ports?

Mode 0 Signup and view all the answers

Which mode is characterized by the use of port C bits for handshake signals before data is transferred?

Mode 1 Signup and view all the answers

What happens when the most significant bit (D7) of the control word in PPI 8255 is set to 0?

It operates in Bit Set Reset mode Signup and view all the answers

What is a limitation of the 8255 PPI?

It provides only three 8-bit ports. Signup and view all the answers

Which of the following is NOT an advantage of using PPI 8255?

High-speed data transfer Signup and view all the answers

What is a common application of the PPI 8255?

Traffic light control Signup and view all the answers

What is the primary function of the 8259 microprocessor?

To handle interrupts from multiple sources. Signup and view all the answers

Which of the following modes allows only port A to work while port B may operate in either Mode 0 or Mode 1?

Mode 2 Signup and view all the answers

How can the interrupt handling capability of the 8259 be increased?

By cascading multiple 8259 chips. Signup and view all the answers

Which is a disadvantage of using the PPI 8255?

Complex programming required for novice users Signup and view all the answers

Which register in the 8259 stores interrupt levels currently being executed?

Interrupt Service Register Signup and view all the answers

How many bits does each port of the PPI 8255 operate with?

8 bits Signup and view all the answers

What feature does the 8251 USART provide for data transmission?

It converts parallel data to serial and vice versa. Signup and view all the answers

What is a significant advantage of the 8251 USART?

It supports both synchronous and asynchronous communication. Signup and view all the answers

What type of power supply is used for the PPI 8255?

+5 regulated power supply Signup and view all the answers

Which application is specifically enhanced by using PPI 8255 with a microprocessor?

Offloading I/O operations from the CPU Signup and view all the answers

The interrupt request register in the 8259 is used for what purpose?

To store requesting interrupt levels. Signup and view all the answers

Which pin is used by the 8259 to connect to other microprocessors for taking interrupt requests?

INTR pin Signup and view all the answers

Which of the following characterizes high functionality relative to PPI 8255?

High-speed data transfer ability Signup and view all the answers

What is the function of a control word in the PPI 8255?

To specify I/O functions for each port Signup and view all the answers

What type of signals does the modem control block manage in the 8251 USART?

Control signals for modulator/demodulator operations. Signup and view all the answers

What type of technology does the PPI 8255 represent in the context of I/O interfaces?

Obsolete technology Signup and view all the answers

What does the Control Logic block in the 8259 do?

It controls the functionality of each block. Signup and view all the answers

What is the role of the data bus buffer in the 8251?

To buffer data for transmission to the CPU. Signup and view all the answers

Which of the following is a feature of the 8259?

It can mask individual bits of the Interrupt Request Register. Signup and view all the answers

What is the maximum number of interrupts that can be achieved by cascading multiple 8259 chips?

64 interrupts Signup and view all the answers

What is a primary disadvantage of the 8251 USART?

It requires complex programming. Signup and view all the answers

What is the maximum operating frequency of the 8253?

2.6 MHz Signup and view all the answers

Which of the following features is available only in the 8254?

Read-Back command Signup and view all the answers

What limits the data transfer rate of the 8251 USART?

Maximum data transfer rate of 115.2 kbps Signup and view all the answers

How many independent counters does the 8253/54 feature?

3 Signup and view all the answers

What characteristic distinguishes the data bus buffer of the 8253/54?

It is a tri-state, bi-directional 8-bit buffer. Signup and view all the answers

Which technology does the 8253 utilize?

N-MOS technology Signup and view all the answers

In which mode are RD and WR signals connected to IOR and IOW?

Peripheral I/O mode Signup and view all the answers

What happens when a counter in the 8253 reaches zero?

It generates a pulse to interrupt the CPU. Signup and view all the answers

Study Notes

Programmable Interfacing Devices: PPI, PIC, USART, PIT

Programmable Peripheral Interface (PPI) 8255: A general-purpose programmable I/O device designed to interface the CPU with external devices like ADC, DAC, and keyboards. It has three 8-bit bidirectional I/O ports (PORT A, PORT B, and PORT C). Each port can be configured as input or output.

PPI 8255 Architecture

8255 consists of 40 pins and operates on a +5V regulated power supply.
Port C is further divided into two 4-bit ports: Port C lower (Cl) and Port C upper (Cu).
Port C can work in either BSR (bit set/reset) mode or in mode 0 of the input/output mode.
Port B can work in either mode 0 or mode 1 of the input/output mode.
Port A can work in mode 0, mode 1, or mode 2 of the input/output mode.
Two control groups: Control group A (Port A and Port C upper) and Control group B (Port C lower and Port B).
Depending on the values of CS', A1, and A0, different ports can be selected and configured as input/output functions or in BSR mode. This is achieved by writing a suitable word to the control register (control word D0-D7).

PPI 8255 Operating Modes

Bit Set / Reset (BSR) Mode: When the MSB of the control word (D7) is 0, the PPI works in BSR mode. Only port C bits are used to set or reset individual bits.
Input/Output Mode: When the MSB of the control word (D7) is 1, the PPI works in input/output mode. This is further divided into three modes:
- Mode 0: Simple input/output function for all three ports (port A, B, C) with no interrupt handling capabilities.
- Mode 1: Handshake I/O mode or strobed I/O mode. Either port A or port B can work as simple input or output, and port C bits are used for handshake signals before data transmission. It has interrupt handling capabilities and input/output are latched.
- Mode 2: Bi-directional data bus mode. Only port A works, and port B can work in either mode 0 or mode 1. Six bits of port C are used as handshake signals. It has interrupt handling capabilities.

PPI 8255 Advantages & Disadvantages

Advantages:*
Versatility: Can be programmed for various modes, making it suitable for diverse systems.
Ease of use: Relatively easy to program, even for beginners.
Compatibility: Widely used and compatible with various devices and software.
Low cost: An affordable option for many applications.
Disadvantages:*
Limited functionality: Less functional compared to newer I/O components, with limitations in data transfer speed and memory capacity.
Limited number of ports: Only provides three 8-bit ports, which may be insufficient for some applications.
Limited resolution: Limited to 8 bits of resolution for each port.
Obsolete technology: An older technology being replaced by newer components.

Programming and Interfacing PPI 8255

Three steps are necessary to communicate with peripherals through 8255:
- Determine the addresses of Port A, B, C, and the control register based on Chip Select Logic and the address lines A0 and A1.
- Write a control word in the control register.
- Write I/O instructions to communicate with peripherals through Port A, B, C.

Common Applications of PPI 8255

Traffic light control: Controlling signal timings.
Generating square waves: Creating specific frequency and duty cycle waveforms.
Interfacing with DC motors and stepper motors: Controlling motor speed and direction.

Programmable Interrupt Controller (PIC) 8259

Designed for microprocessors like 8085 and 8086 to increase interrupt handling capabilities.
Combines multiple interrupt input sources into a single interrupt output, providing 8 interrupts (IR0 to IR7).

PIC 8259 Features

Programmable for either edge-triggered or level-triggered mode.
Allows masking individual bits of the Interrupt Request Register (IRR) to disable specific interrupts.
Cascading multiple 8259 chips allows expanding up to 64 interrupt lines.
Does not require clock cycles for operation.

PIC 8259 Architecture

Data Bus Buffer: Communicates between 8259 and the microprocessor by buffering data and control words.
R/W Control Logic: Controls data flow based on RD and WR signals (active low).
Control Logic: Controls the functionality of the other blocks, including an INTR pin to receive interrupt requests.
Interrupt Request Register (IRR): Stores interrupt requests from different sources.
Interrupt Service Register (ISR): Stores the current interrupt level being processed.
Interrupt Mask Register (IMR): Holds masking bits for disabling specific interrupts.
Priority Resolver: Determines interrupt priority based on all three registers and selects the interrupt with the highest priority for processing.
Cascade Buffer: Allows cascading multiple 8259 chips for extended interrupt capabilities.

Universal Synchronous Asynchronous Receiver Transmitter (USART) 8251

Acts as a mediator between the microprocessor and peripheral devices, converting serial data to parallel and vice versa.

USART 8251 Architecture

Data Bus Buffer: Interfaces the internal data bus of 8251 with the system data bus for data transmission between 8251 and CPU.
Read/Write Control Logic: Controls overall device operation by selecting the register to be accessed (data buffer, control, or status register).
Modem Control (Modulator/Demodulator): Handles communication over telephone lines or cable wires using analog-to-digital and digital-to-analog conversion.
Transmit Buffer: Converts parallel data to serial for transmission.
Transmit Control: Manages data transmission using pins like TXRDY (transmitter ready), TXEMPTY (transmitter empty), and TXC (transmit clock).
Receive Buffer: Buffers received serial data.
Receive Control: Manages data reception using pins like RXRDY (receiver ready), RXC (receive clock), and SYNDET/BD (synchronization/baud rate).

USART 8251 Advantages & Disadvantages

Advantages:*
Versatility: Supports both synchronous and asynchronous communication.
Error detection: Includes parity checking for data accuracy.
Flow control: Regulates data transfer to prevent data loss or overloading.
Compatibility: Compatible with a wide range of microprocessors.
Ease of use: Simple interface pins and registers.
Disadvantages:*
Limited speed: Relatively low maximum data transfer rate.
Limited buffer size: Small internal buffer, which can lead to data loss if not read promptly.
Complex programming: Can be complex to program, requiring attention to timing and other parameters.
Cost: Adds cost to a system, especially with multiple USARTs.
Limited functionality: Lacks more advanced features like DMA or advanced error correction.

Programmable Interval Timer (PIT) 8253/54

Devices designed for microprocessors to perform timing and counting functions using three 16-bit registers.
Each counter has two input pins (CLOCK and GATE) and one output pin (OUT).

8253/54 Architecture

Three independent 16-bit down counters.
Data Bus Buffer: Interfaces with the system data bus.
Read/Write Control Logic: Controls data flow based on RD, WR, CS, and address lines A0 and A1.
Control Word Register: Programmed to specify the counter, mode, and operation (read or write).

8253/54 Pin Description

Three counters (Counter 0, Counter 1, and Counter 2).
Each counter has CLOCK, GATE, and OUT pins.
Data Bus Buffer, Read/Write Logic, and Control Word Register pins.

Differences between 8253 and 8254

8253: Operating frequency 0-2.6 MHz, N-MOS technology, no read-back command.
8254: Operating frequency 0-10 MHz, H-MOS technology, read-back command available.

8253/54 Features

Three independent 16-bit down counters.
Can handle input signals from DC to 10 MHz.
Counters can be programmed for either binary or BCD count.
Compatible with most microprocessors.
8254 has a Read Back command for checking count value, programmed mode, current mode, and counter status.

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Description

Test your knowledge on the Programmable Peripheral Interface (PPI) 8255 and its architecture. This quiz will cover I/O modes, pin configuration, and the operational details of Port A, Port B, and Port C. Ideal for students studying interfacing devices and computer architecture.