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Okay, here are the updated study notes, incorporating the new information while adhering to the specified format:

Verilog (Lecture 2)

• 3'bxyz, is not a legitimate constant in Verilog.
• For sequential blocks, always use non-blocking (<=) assignment.
• For combinational always blocks, use blocking assignment (=).
• A variable can be assigned (LHS) in only one always block.
• Latch Inference will occur when using a signal not in the sensitivity list on the RHS.
• Never put logic on a reset signal.
• An assign statement should use non-blocking (<=) assignment.
• Initial a=1'b0; is not synthesizable (not legal RTL).
• Stick to these guidelines:
  • Stay away from tri-states.
  • Always use full case statement with "x" propagation.
  • Separate sequential and combinational logic.

Synthesizable RTL (Lecture 3)

• No Kahoot this lecture.

Synthesis Part 1 (Lecture 4)

• The basic synthesis flow:
  • Syntax analysis and Library Definition
  • Elaboration and binding, Constraint Definition
  • Pre-mapping Optimization, Technology Mapping
  • Post-mapping Optimization, Report and Export
• Standard cells generally have:
  • SITE
  • Number of tracks
  • Fan-In
  • Nwell connection on sides
• Commonly found in a standard cell library:
  • Level Shifter
  • Delay Cell
  • Negative-edge Flip Flop
• Bonus cells are cells without functionality that fill in empty spaces.
• Boolean function of an OAI21 gate: ((A0+ A1) • Β0)!
• Part of an IP library:
  • CCS/ECSM models
  • NMOS models
  • DRC Rule File
  • Verilog behavioral models
  • Spice models
  • Full layout (GDS)
• Antenna information is not usually inside the LEF file of a standard cell.
• Technology LEF is used for:
  • Providing basis for parasitic extraction
  • Defining the SITES to be used
  • Routing metal layers according to DRCs
  • Creating Vias
• Parameters affecting the delay of a cell in a .lib file: Output Transition and Input Load

Synthesis Part 2 (Lecture 5)

• .sdc file of constraints is not required to successfully elaborate a design.
• The cost function of "Espresso": Minimize the number of literals in the output functions.
• Each node of a BDD represents a specific Boolean function, and a BDD is a directed acyclic graph (DAG).
• Tree-covering the netlist with simple weighted gates is optimal for Technology Mapping.
• Common post-synthesis optimization heuristic:
  • Swap connections on commutative pins
  • Buffering a high-fanout logic gate
  • Adding pipeline stages
  • Fix clock skew with delay buffers
  • Cloning a high-fanout logic gate
• Types of IPs found in DesignWare:
  • Radix-4 Booth multiplier
  • 32-bit barrel shifter
  • 12-bit SAR ADC
  • 256x32 cell SRAM array
• Clock gating helps save power.
• Avoid clock gating when enable logic goes to very few flip-flops.
• Delays are calculated according to a rough place and route of the netlist when using Topographical Synthesis.
• The correct order of the synthesis process: Read RTL, Read Libs, Elaborate, Pre-map Opt, Read SDC, Map, Post-map Opt

Static Timing Analysis (Lecture 6)

• Synchronous design helps eliminate races.
• Synchronous design is the only way to implement digital systems.
• T_hold parameter is demonstrated in the illustration.
• Apply retiming if a chip is fabricated with negative hold slack
• Min delay (hold) constraints set the maximum frequency.
• It verifies correct circuit functionality, which is not an advantage of STA
• The critical path: A, d, f, g, j
• Correct create_clock Command is: Create_clock “clk” -freq 1 GHz -ports [get_ports CLK]
• Clock jitter is defined via Set_clock_uncertainty in the SDC
• Output delay and output capacitance (load) are needed to model output paths in SDC.
• A max delay timing report is shown.

Moving to the Physical Domain (Lecture 7)

• Floorplan creation: after Synthesis and before Placement
• NLDM .lib models are not defined when moving from Synthesis to Floorplanning.
• The displayed floorplan: Core Limited
• Not a reason to limit utilization to be under 100%: To leave room for routing power rails.
• May cause a short between similar references if the netlist is not Uniquified.
• Guidelines for a good floorplan:
  • Move pins away from corners
  • Try to make a big continuous area for standard cell placement
  • Put halos around SRAMs
• Defining timing constraints on the I/O pins of the blocks is what an ILM is used for.
• Measure the ratio between the current density and size of the wire to check for electromigration problems.
• Techniques to limit static (IR) and dynamic (di/dt) drop:
  • Add decap cells wherever possible
  • Route power line on thick (top) metals
  • Connect power supplies from several I/O pads
  • Use a dense power mesh
• All of the above, is a clear and direct consequence of a poorly planned power distribution network.

Placement (Lecture 8)

• The biggest contributor to place and route complexity: Number of instances.
• The HPWL of the green square is 6.
• Simulated annealing allows a positive AL.
• The temperature (T) affects the probability of choosing a worse solution within the simulated annealing algorithm.
• A clique model is used in quadratic placement to support nets with a large fan-out
• 2⇔5, wire is probably going to be the longest.
• Recursive partitioning resolves the gate clustering phenomenon.
• Placement legalization often uses simulated annealing in current tools.
• Power is not a placement optimization target.
• Timing is estimated during placement: Based on gate delays and virtual routes
• "Congestion" occurs when there are more required routing tracks than available tracks.

Clock Tree Synthesis (Lecture 9)

• Negative Skew is shown.
• Hold: 2, Setup: 3 is shown.
• Line 1 represents "useful skew".
• Different number of buffers in the clock path to registers causes clock skew.
• Deep pipelines technology trends impede the clock tree construction and functionality.
• "CK input of a flip flop, is an implicit stop pin (clock sink).
• Try to reach the pin at 100ps is what the CTS will do.
• Clock gating, is what is not a method of clock tree optimization?
• Paths benefit from positive skew that are defined with set_input_delay after CTS
• Shield clock nets to make them less susceptible to noise.

Routing (Lecture 10)

• A band-gap filter is not a part of a PLL
• High mtbf isn't a possible consequence of non-treated clock-domain crossing.
• F = 1 mhz, f_d = 0.3 mhz, t_w = 30ps - the rate of metastability is 9 × 10^6.
• Starts with detailed routing and then goes to global routing, which is incorrect about the routing algorithm? Backtrace, stage of maze routing comes next is.
• What is the cost of routing to the first target in the multi-target net shown in the picture? 5
• South, is the direction that is cheapest?
• Notch spacing, kind of correction is shown,.
• Violation: Speed up - hold, slow down - setup
• Solutions:
  • Upsizing the victim driver
  • Increasing wire spacing
  • Adding additional power stripes
  • Choosing a copper interconnect layer

Packaging, I/O (Lecture 11)

• The path from the board (top) to the chip (bottom): pin/ball
• Most important requirements of a package:
  • Pin count
  • Heat removal
  • Price
  • Testing
  • Reuse
  • Flexibility
• Packages (most expensive to cheapest):
  • ball grid array
  • pin grid array
  • quad flat package
  • dual-inline package
• Flip chip properties compared to wire bonding: Lower pin capacitance and Faster to connect to chip.
• A ball of solder on the chip is a bump.
• Analog i/o buffer type of circuit is shown in the picture?
• What is the job of the secondary ESD elements? To provide first protection until the primary esd turns on.
• Analog i/o circuit, provides the low voltage to the esd diodes?.
• In-line type of pad configuration is shown.
• A chip that is a substrate for additional chips, is an interposer

Signoff (Lecture 12)

• Maximum delay arc through a logic gate causes a delay not part of the 8 margin as presented in the timing constraint equations.
• Setup timing check is affected by the command, set_timing_derate -max -early 0.9 -late 1.2
• Ocv is the most pessimistic.
• Rcworst, extract option fits the following picture.
• Related to aging:
  • Hci
  • Nbti
• Add moscaps between vdd and gnd, methods are used to add decoupling capacitance?
• Lec, not a step in the physical verification process
• Acronym this course did not mentioned this course: Rcm
  • The following were the tools that was run:
• Innovus
• Genus
• Voltus
• Tempus
• Xcelium
• Name of chip: Itanium