Multi-processor and Flynn's Taxonomy Flashcards

Questions and Answers

What does SISD stand for?

Single Instruction Multiple Data

Single Instruction Single Data (correct)

Multiple Instruction Multiple Data

Multiple Instruction Single Data

What are some characteristics of SIMS?

Array processors, GPUs, runs the same instruction on multiple data streams in parallel.

What does MIMD stand for?

Multiple Instruction Multiple Data

What is MIPS?

MIPS is a general purpose register architecture with explicit operands that are either registers or memory locations. Signup and view all the answers

What are some advantages of using MIPS?

Registers are faster and memory traffic is reduced. Signup and view all the answers

What are the two classes of register computers?

Register-memory and load-store. Signup and view all the answers

In the classification (m,n), what do m and n represent?

m is maximum number of memory addresses, n is the required number of operands in an ALU instruction. Signup and view all the answers

What is MIPS classified as (m,n)?

(0,3) Signup and view all the answers

An ISA is said to be orthogonal if it lacks redundancy.

True Signup and view all the answers

What three addressing modes does MIPS support?

Register, Immediate, and Displacement. Signup and view all the answers

How many general-purpose registers does MIPS64 have?

32 64-bit General Purpose registers and 32 64-bit Floating Point registers. Signup and view all the answers

What is the format of Assembly language?

ALU Instructions: Operator destination, source, source; Non-Jump Instructions: Operator destination, source. Signup and view all the answers

Study Notes

Flynn's Taxonomy

Categorizes parallel computing architectures into four types: SISD, SIMD, MISD, and MIMD.
Useful for understanding how different systems execute instructions and manage data.

SISD (Single Instruction, Single Data)

Involves individual CPU cores with no parallelism in execution or data streams.
Pipelining does not qualify as parallelism in this context.

SIMD (Single Instruction, Multiple Data)

Utilizes array processors and GPUs to execute the same instruction across multiple data streams concurrently.
Ideal for tasks like image processing and scientific simulations where uniform operations are applied to large datasets.

MISD (Multiple Instructions, Single Data)

An example includes space shuttle flight controllers that execute multiple instructions on the same dataset.
Primarily used for fault tolerance, not widespread in general-purpose processing.

MIMD (Multiple Instruction, Multiple Data)

Employed in supercomputers and distributed systems.
Capable of executing different instructions on different data streams simultaneously, enhancing computational efficiency.

MIPS (Microprocessor without Interlocked Pipeline Stages)

A general-purpose register architecture emphasizing explicit operands: registers or memory locations.
Promotes high-speed operations through direct access to registers.

Advantages of MIPS

Faster access to registers compared to memory.
Reduces memory traffic by keeping operands in registers, leading to increased efficiency.

Classes of Register Computers

Register-memory: Found in architectures like IA32, allows memory access as part of any instruction.
Load-store: MIPS architecture, restricts memory access strictly to load or store instructions.

Classification (m, n)

'm' represents the maximum number of memory addresses.
'n' indicates the required number of operands in an ALU instruction.

MIPS (0, 3) Classification

Referred to as "pure RISC" architecture.
Stresses the importance of a simple instruction set and efficient pipelining, enhancing speed and performance.

Orthogonality of ISA

An Instruction Set Architecture (ISA) is orthogonal when it lacks redundancies, ensuring every task can be completed with a unique instruction.
Guarantees no interference between instructions, allowing for cleaner and more reliable programming.

MIPS Addressing Modes

Supports three primary addressing modes: Register, Immediate, and Displacement for flexibility in accessing data.

MIPS64 Register Types

Contains 32 General Purpose (GPR) registers (R0 - R31), each 64 bits in size.
Includes 32 Floating Point (FPR) registers (F0 - F31), also 64 bits.
R0 is designated as a constant zero register, simplifying certain operations.

Assembly Language Format

Organizes ALU instructions in the format: Operator destination, source, source.
Non-jump instructions follow a simplified format: Operator destination, source, promoting clarity in code structure.

Description

Test your knowledge on multi-processor architectures and Flynn's Taxonomy through these flashcards. Each card includes definitions and classifications to help you understand the nuances of ISA design. Perfect for students exploring advanced computer architecture concepts.