CPU Architecture: Flynn's Taxonomy

CPU Architecture

• ** Flynn's Taxonomy**: classification of CPU architectures based on the number of instruction streams and data streams:
  • SISD (Single Instruction, Single Data): single instruction operates on single data element (traditional von Neumann architecture)
  • SIMD (Single Instruction, Multiple Data): single instruction operates on multiple data elements (vector processing)
  • MISD (Multiple Instruction, Single Data): multiple instructions operate on single data element (rarely used)
  • MIMD (Multiple Instruction, Multiple Data): multiple instructions operate on multiple data elements (parallel processing)
• CPU Components:
  • Control Unit: retrieves and decodes instructions, generates control signals
  • Arithmetic Logic Unit (ALU): performs arithmetic and logical operations
  • Registers: small amount of on-chip memory for storing data and instructions

Instruction Pipeline

• Instruction Pipeline Stages:
  1. Instruction Fetch: retrieve instruction from memory
  2. Instruction Decode: decode instruction into opcode, operands, and control signals
  3. Operand Fetch: retrieve operands from registers or memory
  4. Execution: execute instruction using ALU
  5. Memory Access: access memory for load/store operations
  6. Write Back: write results back to registers
• Pipeline Hazards:
  • Structural Hazards: conflicts between instructions for shared resources (e.g., registers)
  • Data Hazards: dependencies between instructions for data operands
  • Control Hazards: conflicts between instructions for control flow (e.g., branches)
• Pipeline Optimization Techniques:
  • Instruction-Level Parallelism (ILP): execute multiple instructions concurrently
  • Out-of-Order Execution: execute instructions out of original order to reduce dependencies
  • Register Renaming: rename registers to reduce dependencies and improve ILP

CPU Architecture

• Flynn's Taxonomy categorizes CPU architectures into four types based on the number of instruction streams and data streams.
• SISD (Single Instruction, Single Data) architecture has a single instruction operating on a single data element, typical of traditional von Neumann architecture.
• SIMD (Single Instruction, Multiple Data) architecture has a single instruction operating on multiple data elements, used in vector processing.
• MISD (Multiple Instruction, Single Data) architecture has multiple instructions operating on a single data element, rarely used.
• MIMD (Multiple Instruction, Multiple Data) architecture has multiple instructions operating on multiple data elements, used in parallel processing.

CPU Components

• The Control Unit retrieves and decodes instructions, generating control signals.
• The Arithmetic Logic Unit (ALU) performs arithmetic and logical operations.
• Registers are small amounts of on-chip memory for storing data and instructions.

Instruction Pipeline

• The Instruction Pipeline is divided into six stages: Instruction Fetch, Instruction Decode, Operand Fetch, Execution, Memory Access, and Write Back.
• Instruction Fetch retrieves an instruction from memory.
• Instruction Decode decodes the instruction into an opcode, operands, and control signals.
• Operand Fetch retrieves operands from registers or memory.
• Execution executes the instruction using the ALU.
• Memory Access accesses memory for load/store operations.
• Write Back writes results back to registers.

Pipeline Hazards

• Structural Hazards occur when instructions conflict for shared resources, such as registers.
• Data Hazards occur when instructions have dependencies for data operands.
• Control Hazards occur when instructions conflict for control flow, such as branches.

Pipeline Optimization Techniques

• Instruction-Level Parallelism (ILP) executes multiple instructions concurrently.
• Out-of-Order Execution executes instructions out of their original order to reduce dependencies.
• Register Renaming renames registers to reduce dependencies and improve ILP.