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used when one unit is sending address info(location) of data residing in memory to another unit
used when one unit is sending address info(location) of data residing in memory to another unit
Send IAC contents to MAR perform Memory Read Operation and get the instruction
Send IAC contents to MAR perform Memory Read Operation and get the instruction
special purpose, high-speed temporary memory units used by processor holding data
special purpose, high-speed temporary memory units used by processor holding data
science of selecting and interconnecting hardware components to create computer that meet functional, performance and cost goals
science of selecting and interconnecting hardware components to create computer that meet functional, performance and cost goals
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rate which processor process info and measured in millions cycle per second(Megahertz)
rate which processor process info and measured in millions cycle per second(Megahertz)
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any peripheral used to provide data and control signals to information processing system such as computer or other information appliance
any peripheral used to provide data and control signals to information processing system such as computer or other information appliance
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fastest cache and usually comes within processor chip istelf. Range from 8KB to 64KB. Uses high-speed SRAM
fastest cache and usually comes within processor chip istelf. Range from 8KB to 64KB. Uses high-speed SRAM
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dOnly Memory (EPROM) erased by exposure to strong uultraviolet light then rewritten with process that again needs higher than usual voltage applied
dOnly Memory (EPROM) erased by exposure to strong uultraviolet light then rewritten with process that again needs higher than usual voltage applied
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provide location of data(in register) to be fetched from memory to address bus and data carries required data to processor
provide location of data(in register) to be fetched from memory to address bus and data carries required data to processor
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brain of computer. Bus master decides who should control bus when more than one unit wants bus at same time
brain of computer. Bus master decides who should control bus when more than one unit wants bus at same time
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Instruction fetched and executed by control unit one by one.
Instruction fetched and executed by control unit one by one.
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Determine operand address
Determine operand address
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interconnects processor, memory and I/O devices
interconnects processor, memory and I/O devices
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contains electronic circuits necessary to perform Arithmetic and logical operations
contains electronic circuits necessary to perform Arithmetic and logical operations
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not found nowadays as functuion is replaced by L2. Found on motherboard rather tha processor. Kept between Ram and L2.
not found nowadays as functuion is replaced by L2. Found on motherboard rather tha processor. Kept between Ram and L2.
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piece of computer hardware used to communicate the results of processed data to user
piece of computer hardware used to communicate the results of processed data to user
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written to programmed via special device(PROM Programmer)
written to programmed via special device(PROM Programmer)
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Fetch operands one by one, from Memory or form Registers and supply operands to ALU
Fetch operands one by one, from Memory or form Registers and supply operands to ALU
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responsible for directing & coordinating computer system activities. Does not execute instructions. It tells other part of computer what to do. Determines movement between main memory & arithmetic logic unit as well as control signals between CPU and I/O
responsible for directing & coordinating computer system activities. Does not execute instructions. It tells other part of computer what to do. Determines movement between main memory & arithmetic logic unit as well as control signals between CPU and I/O
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similar semiconducor to EPROM, but allows its entire contents to be electrically erased, then rewritten electrically, so they need not be removed from computer
similar semiconducor to EPROM, but allows its entire contents to be electrically erased, then rewritten electrically, so they need not be removed from computer
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piece of very fast memory made from high-speed static RAM that reduces the access time of data. Very expensive and generally incorporated in processor, where valuable data and program segments are kept
piece of very fast memory made from high-speed static RAM that reduces the access time of data. Very expensive and generally incorporated in processor, where valuable data and program segments are kept
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comes between L1 and RAM and bigger than primary cache
comes between L1 and RAM and bigger than primary cache
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rate which processor process info and measured in millions cycle per second(Megahertz)
rate which processor process info and measured in millions cycle per second(Megahertz)
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responsible for making CPU/ memory and I/O work together as functional system. Determine instruction according tooperation type(Read or Write)
responsible for making CPU/ memory and I/O work together as functional system. Determine instruction according tooperation type(Read or Write)
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Analyze the OPCODE and determine type of instructions
Analyze the OPCODE and determine type of instructions
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set of wires used for interconnection of different units of a computer system.
set of wires used for interconnection of different units of a computer system.
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consists instruction and data
consists instruction and data
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Modern type of EEPROM. Use on transistor per memory cell and come in capacities ranging from 1MB to 32GB. Read time smaller(tens of nonseconds) compared write time(tens of microseconds)
Modern type of EEPROM. Use on transistor per memory cell and come in capacities ranging from 1MB to 32GB. Read time smaller(tens of nonseconds) compared write time(tens of microseconds)
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the less Number of hertz , the faster
the less Number of hertz , the faster
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larger bus width, the faster. The grater amount of data can travel on it in given amount of time
larger bus width, the faster. The grater amount of data can travel on it in given amount of time
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speed of computer system
speed of computer system
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used when unit is sending data, instruction/ command code to some other units
used when unit is sending data, instruction/ command code to some other units
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hold bi-directional relationship with control and data bus
hold bi-directional relationship with control and data bus
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data stored can't modified. Can modify only slowly. Mainly used to distribute. Random access and Non-volatile.instructions build into electronic circuits of chip(firmware)
data stored can't modified. Can modify only slowly. Mainly used to distribute. Random access and Non-volatile.instructions build into electronic circuits of chip(firmware)
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commuication with processor and memory is unidirectional
commuication with processor and memory is unidirectional
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Do the required or logical operation for instruction
Do the required or logical operation for instruction
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Study Notes
Computer Architecture and Memory
- Memory Address Register (MAR) receives IAC contents and performs a Memory Read Operation to fetch an instruction.
- The science of selecting and interconnecting hardware components to create a computer that meets functional, performance, and cost goals is known as computer architecture.
- The processor's speed is measured in millions of cycles per second (Megahertz).
Cache Memory
- Level 1 (L1) cache is the fastest cache, usually located within the processor chip, and ranges from 8KB to 64KB in size. It uses high-speed SRAM.
- Level 2 (L2) cache is larger than L1 cache and is located between the primary cache and RAM.
Input/Output (I/O) Devices
- Any peripheral device that provides data and control signals to an information processing system, such as a computer or other information appliance, is an I/O device.
- The communication between the processor and I/O devices is unidirectional.
Memory Types
- EPROM (Erasable Programmable Read-Only Memory) is erased by exposure to strong ultraviolet light and then rewritten with a process that requires higher-than-usual voltage applied.
- PROM (Programmable Read-Only Memory) is written to and programmed via a special device (PROM Programmer).
- EEPROM (Electrically Erasable Programmable Read-Only Memory) is similar to EPROM, but allows its entire contents to be electrically erased and rewritten, so they do not need to be removed from the computer.
- Flash memory is a modern type of EEPROM, using one transistor per memory cell, and comes in capacities ranging from 1MB to 32GB.
Bus and Interconnects
- The bus is a set of wires used for interconnection of different units of a computer system, consisting of instruction and data buses.
- The bus width determines the speed of the computer system, with a larger bus width allowing for more data to travel on it in a given amount of time.
- The control unit is responsible for directing and coordinating computer system activities, determining movement between main memory and the arithmetic logic unit, as well as control signals between the CPU and I/O.
Control Unit and Processor
- The control unit is the brain of the computer, deciding who should control the bus when more than one unit wants to use it at the same time.
- The control unit is responsible for making the CPU, memory, and I/O work together as a functional system.
- The processor speed is measured in millions of cycles per second (Megahertz).
- The Arithmetic Logic Unit (ALU) performs the required or logical operation for an instruction.
Instruction Cycle
- The instruction cycle involves fetching instructions one by one, determining the operand address, and executing the instruction.
- The control unit analyzes the opcode and determines the type of instruction.
- Fetch operands one by one, from memory or from registers, and supply operands to the ALU.
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Description
Memory Addressing Quiz: Test your knowledge on the process of sending address information from one unit to another in order to access data residing in memory.