Linear Integrated Circuits: Manufacturing Process

EGEC4220 Linear Integrated Circuits - Learning Outcome 1

• This course aims to impart knowledge of linear integrated circuits, their functions, and applications in telecommunications.
• Students will use simulation software to reinforce theoretical and practical skills.
• Upon completion of the course, students should be able to illustrate IC manufacturing process.

Course Details

• The course code is EGEC4220.
• The course name is Linear Integrated Circuits.
• The academic year is 2024-25.
• The course level is BTech.
• It has 3 credit hours.
• Contact hours include 2 hours of theory per week and 2 hours of practical application per week.
• To pass, a grade of C/67 is required.
• Pre-requisites include EGEC3110 Electronics II.
• Dr. Sindhu S Nair teaches the course and their office is at EE204 Staff Room.
• Office hours are from 10:00 AM to 12:00 AM on Tuesdays and Thursdays.

Course Objectives and Learning Outcomes

• An objective is to enable students to discuss the manufacturing process of ICs.
• Students should be able to explain op-amp characteristics and compensation parameters.
• An objective is to design and analyze linear and non-linear circuits using Op-Amps.
• Students should be able to design and simulate real-time application circuits using special function ICs.
• Students should be able to apply knowledge of differential amps and analyzing basic building blocks, understanding characteristics of op amp
• Students should be able to construct analog circuits using PLL, VCO, IC 565, AM/FM detection, FSK modulation/demodulation, and Frequency Synthesizing/clock synchronization.
• Students should be able to analyze and design different types of A/D and D/A converters.
• The production of electronics influences the global heating and consumption of natural resources, and how life-cycle analysis and the global aims can be used.

Assessment Plan

• There is a mandatory quiz equating to 10%
• Attendance and HSE equates to 5% of the final grade.
• Aims/Objectives, procedure, table, graphs etc equates to 10% of the final grade
• Lab test equates to 10% of the final grade.
• A case study is 10% of the final grade.
• The midterm exam is 20% of the final grade.
• The final exam is 35% of the final grade.

Course Outline

• Introduction to Integrated Circuits (ICs)
• Reasoning behind using Silicon
• Silicon purity requirements
• IC classification criteria
• Scale of integration
• Types of ICs
• Advantages and disadvantages of ICs
• Steps involved in IC fabrication.

Introduction

• Silicon is a commonly used semiconductor material in semiconductor devices and integrated circuits and is mostly used as a substrate material.
• Solar cells made of silicon wafers are affordable for practical applications.
• Compound semiconductors IV-IV, III-V, and II-VI, attract interest in research and industry.
• Compound semiconductor III-V has LED and LASER applications using gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN).
• Most optoelectronic devices use III-V compounds.
• Microminiaturization of electronics, application to computers, communications are major innovations of the twentieth century.
• New applications became possible because of this compared to discrete devices.
• Integrated circuits on silicon wafers reduce costs and increase reliability.

Why Silicon?

• Semiconductor devices come in discrete units and integrated units.
• Discrete Units: Diodes, transistors, etc.
• Integrated Circuits: Use discrete units to make one device.
• Monolithic IC: Transistors, diodes, and resistors are integrated on the same chip.
• Hybrid IC: Discrete elements connect to a chip with external discrete components.
• Silicon forms a superior stable oxide (SiO2) with superb insulating properties and is available in large quantities in sand.
• GaAs crystals have a high density of crystal defects that limit device performance.
• Si and Ge do not decompose during processing unlike GaAs compound semiconductors.
• Silicon is the major semiconductor in the industry currently

Purity of Silicon

• The starting material for devices and ICs is a circular slice called a wafer
• Wafers range from 10-20 cm, up to 30 cm in diameter.
• Silicon is abundant as an oxide in sand and quartz.
• Silicon must be:
  • Crystalline
  • Very pure
  • Free of defects
  • Uncontaminated.

Classification of ICs

• By Scale of Integration:

  • SSI: < 10 components
  • MSI: 10-100 components
  • LSI: 100-1000 components
  • VLSI: 1000-10,000 components
  • ULSI: >100,000 components

• By Type of Signal:

  • Digital ICs
  • Analog / Linear ICs

• By Type of Fabrication Techniques:

  • Monolithic ICs
  • Thick-Thin ICs
  • Hybrid ICs

Scale of Integration

• The first semiconductor IC chip held one diode or transistor.
• Technology advanced to enable more transistors to be added.
• Small-scale integration (SSI) arrived first, improved techniques led to large-scale integration (LSI) with hundreds of logic gates.

Types of Integrated Circuits

• Monolithic IC:

  • The entire circuit is on a single semiconductor chip.
  • It consists of active and passive components.
  • Microprocessors and memory ICs are examples of monolithic ICs.

• Hybrid IC:

  • The electronic circuit is integrated on a ceramic substrate with components enclosed in a single package.
  • It consists of monolithic ICs connected by metallic interconnects on a substrate.
  • Hybrid IC streamlines connections between semiconductor chips by replacing wire bonding through a technology bonding various substrates at the die or wafer level.
  • The process allows increase in communication bandwidth and higher system yield and is accelerated, streamlined, and less costly process.

Advantages and Disadvantages of ICs

• Advantages:

  • Small size due to reduced dimensions
  • Low weight due to small size
  • Low power requirement from lower dimensions and threshold
  • Low cost from large-scale production
  • High reliability due to solder joint absence
  • Facilitates integration of many devices
  • Improved high-frequency performance

• Disadvantages:

  • IC resistors have limited range
  • Inductors (L) can not be formed
  • Transformers can not be formed

Steps Involved in IC Fabrication:

• Silicon wafer (substrate) preparation.
• Epitaxial growth.
• Oxidation.
• Photolithography.
• Diffusion.
• Ion implantation.
• Isolation technique.
• Metallization.
• Assembly processing & packaging.

Crystal Growth and Wafer Preparation

• Crystal growth and wafer preparation is the most fundamental step in device fabrication, and various crystal growth techniques are used.
• Using the Czochralski Process, pure semiconductor grade silicon is melted in a quartz-lined crucible where purity is key.
• The melt is at 1690K, slightly above silicon's melting point of 1685K.
• A seed crystal is dipped into the melt and slowly pulled out; this step is crucial for the single-crystal structure formation.
• A small seed crystal of silicon is attached to the top of a rod and lowered into a crucible of molten silicon to which acceptor impurities have been added.
• A single p-type or n-type crystal ingot of the order of several inches has grown as the rod is very slowly pulled out of the 'melt' under carefully controlled conditions
• The ingot is sliced into round wafers for integrated component fabrication.
• One side of each wafer is lapped and polished to eliminate surface imperfections.
• The remaining bulk of melt has the crystal diameter decreased until it has a point contact with the melt, during the final process.
• The ingot is cooled and removed to be made into wafers
• The ingots have diameters as large as 200mm, with the latest ones approaching 300mm; the ingot length is of the order of 100cm.
• Slicing wafers requires precision equipment to produce flat faces and smooth surfaces.
• Wafer processing includes lapping, polishing, and chemical etching.
• Lastly, wafers are cleaned, rinsed and dried.

Epitaxial Growth

• Epitaxial growth uses processes that yield the hydrogen reduction of silane, and these include silicon tetrachloride
• As the source for silicon.
• Silane has two advantages: lower temperature and faster growth rate.
• The chemical reaction for the hydrogen reduction of SiCl4 is: SiCl4 + 2H2 (1200 °C) results in Si + 4HCl.
• The chemical reaction for the hydrogen reduction of SiH4 is: SiH4 (H2 atmosphere, 1000°C) results in Si +2H2
• N-type epitaxial layers, a few nanometers to micrometers thick, grow on a p-type substrate with approximately few cm resistivity.
• Phosphine (PH3) or Diborane (B2H6) it is essential to introduce impurities for n-type or p-type doping. -The process steps include:
  • Heating the wafer to 1200°C
  • Turning on H2 to reduce SiO2
  • Turning on anhydrous HCl to vapor-etch the surface
  • Turning off HCl
  • Dropping the temperature to 1100°C
  • Turning on silicon tetrachloride (SiCl4)
  • Introducing a dopant

3. Oxidation for Isolation

• Silicon naturally grows an oxide layer, SiO2, for surface passivation.
• Using masking techniques combined with n-type silicon wafers, impurities used in doping do not penetrate the surface.
• Hydrogen fluoride (HF) etches the oxide layer.
• During wet oxidation thermal oxidation of silicon occurs in the presence of water where : Si + 2H2O → SiO2 + 2H2
• Oxide layers are 0.02 mm to 2 mm thick; thickness depends on, process temperature, impurity concentration, and processing time.
• Dry oxidation is represented by Si + O2 → SiO2.

4. Photolithography

• The wafer is baked at 100°C to solidify the resist.
• The reticle is placed and computer-aligned on the wafer.
• The reticle exposes the wafer to UV light; opaque regions remain unaffected.
• Photoresist is chemically removed, exposing the silicon dioxide.
• Hydrofluoric acid removes the exposed silicon dioxide.
• The opaque part of the reticle regions are still with photoresist as well as silicon dioxide.
• The photoresist is removed with a solvent exposing silicon dioxide.
• Etching: Selective material removal that creates semiconductor regions from metal or silicon dioxide.
• Dry Etching processes use radio-frequency electric fields and a gas such as argon to bombard the surface with ions.
• Wet Etching processes use chemical solutions at predetermined temperatures to immersed to etch in all directions.

5. Diffusion

• Diffusion occurs in predeposition and drive-in steps.
• A high concentration of dopant atoms at the silicon surface is exposed to a vapor containing the dopant at approximately 1000°C; ion implantation is employed.
• Silicon atoms move, creating vacancies and breaking bonds around 1000°C.
• Diffusion is used to drive impurities into the surface without adding more.
• Common dopants are boron for P-type layers and phosphorus, antimony, and arsenic for N-type layers.
• Wafers are in a quartz furnace tube heated by resistance heaters in a quartz carrier, and the quartz carrier is known as a boat.

6. Ion Implantation

• Arc discharge in a gas, e.g., phosphine (PH3), generates ions.
• Ions accelerate via electric fields, acquiring 20keV energy, and are passed through magnetic fields.
• The magnetic field separates unwanted impurities from the dopant ions based on mass.
• Ions are accelerated to reach hundreds of keV and focused on the silicon wafer.
• Advantages of ion implantation include:
  • Precisely controlled doping levels
  • Easy regulation of dopant depth
  • High dopant purity
  • Controlled doping uniformity
  • Minimized impurity movement due to low temperature

7. Isolation Techniques

• It is necessary to provide electrical isolation between different components in IC's.
• p-n junction and dielectric isolation are the two used techniques.
• P-N JUNCTION ISOLATION: P type impurities, in this case, are diffused into an n type epitaxial layer.
• During dielectric isolation a solid dielectric layer of SiO2 surrounds components which provides physical and electrical isolation, such as ruby.
• The associated capacitance is negligible and therefore the isolating dielectric layer is thick enough to be considered negligible.
• It’s possible to fabricate NPN and PNP transistors on the same Si substrate

8. Metallization

• This involves producing a thin metal film layer to create an interconnection between various components.
• Metallization takes place towards the end of the fabrication process and includes deposition over a layer of Al over silicon for the die interconnect to occur
• Aluminum is a good conductor as well as it makes good mechanical bonds with silicon, forms a low resistance contact as well as it’s easily patterned and can be applied using deposition and etching.

9. Assembly Processing & Packaging:

• Hundreds of chips are contained within each wafer and they’re separated and packaged via scribing and cleaving
• The method uses a diamond tipped tool, which is then used to cut around each rectangular grid which then divides the die.
• There are three package configurations:
  • Metal can package.
  • Ceramic flat package.
  • Dual in line package.
• The last step of this process is packaging, based on product type or manufacturer
  • Small wires are bonded to connect pads to the external connection pins.
  • The most common packaging is dual input packaging(DIP).
  • The Czochralski process is used to design wafers.
  • Testing is performed before packaging.

Learn about linear integrated circuits, their functions, and telecommunications applications. This lesson will cover the IC manufacturing process, reinforcing theoretical knowledge with practical simulation software. Course code: EGEC4220.