Interrupts in Microprocessors

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Questions and Answers

What happens to the contents of W, BSR, and STATUS registers during high priority interrupts?

They are stored in external memory.

They are automatically saved into shadow registers. (correct)

They are cleared and not saved.

They are ignored and not affected.

Which of the following scenarios will trigger an interrupt in PIC18 microcontrollers when using PORTB pins as digital inputs?

Constant high voltage on RB0/INT0.

Change of logic level on RB0/INT0. (correct)

No change in voltage levels on RB1/INT1.

Only falling edge detection on RB2/INT2.

How is the counting time determined in a timer?

By dividing the clock period by the count interval.

By adding the clock period to the count interval.

By subtracting the count interval from the clock period.

By multiplying the count interval by the clock period. (correct)

What distinguishes a free-running timer from a sequence controlled counter?

A free-running timer increments/decrements every clock interval. Signup and view all the answers

What is the main function of a prescaler in timer circuits?

To reduce a high frequency signal to a low frequency using integer division. Signup and view all the answers

What is the role of the TMR0ON control bit in the T0CON register?

It enables or disables Timer0. Signup and view all the answers

Which Timer configuration features a prescaler but does not use a postscaler?

Timer0 with 1:16 prescaler and no postscaler. Signup and view all the answers

In the T0CON register, what does the T0SE bit control?

The increment behavior on clock transitions. Signup and view all the answers

Which Timer is configured as a 16-bit up counter with an interrupt on overflow?

Timer1. Signup and view all the answers

What happens when the PSA bit in the T0CON register is set to 1?

The Timer0 prescaler is not assigned. Signup and view all the answers

What initiates a hardware interrupt?

Requests from external peripherals Signup and view all the answers

What happens to the processor when it receives an interrupt?

It pauses execution and redirects to an Interrupt Service Routine. Signup and view all the answers

Which type of interrupt cannot be disabled?

Non-maskable interrupt Signup and view all the answers

What is an Interrupt Service Routine (ISR)?

A sequence of instructions executed when a specific interrupt is raised. Signup and view all the answers

What is the primary benefit of using interrupts in a microprocessor system?

Improved efficiency by allowing multitasking and real-time responses. Signup and view all the answers

How does the processor determine which interrupt service routine to execute?

By identifying the peripheral that raised the interrupt. Signup and view all the answers

What instruction is typically used to conclude the execution of an ISR?

Return from Interrupt (RETFIE) Signup and view all the answers

What occurs when multiple interrupt requests arrive simultaneously?

Priority schemes in the processor decide the order of servicing. Signup and view all the answers

What is the function of the GIE/GIEH bit in the INTCON register?

Enables all interrupts when IPEN=0 Signup and view all the answers

What happens when the PEIE/GIEL bit is set to 0 with IPEN=0?

All peripheral interrupts are disabled Signup and view all the answers

What is the purpose of the TMR0IE bit?

Enables TIMER0 overflow interrupt Signup and view all the answers

What does a TMR0IF value of 1 indicate?

TIMER0 has overflowed Signup and view all the answers

When INT0IE is set to 1, what is the expected state for the INT0 external interrupt?

INT0 external interrupt is enabled Signup and view all the answers

What effect does setting RBIE to 1 have?

Enables the RB port change interrupt Signup and view all the answers

In the INTCON2 register, what does the INTEDG0 bit determine?

The edge sensitivity for INT0 interrupt Signup and view all the answers

If INT1IE is set to 0, what does this imply?

INT1 external interrupt is disabled Signup and view all the answers

What do the bits INT2IP and INT1IP control?

The priority level of INT1 and INT2 interrupts Signup and view all the answers

What does the T0PS2:T0PS0 bits in the T0CON register determine?

Timer0 prescaler value Signup and view all the answers

What is indicated by a value of 1 in the TMR0IF flag bit?

Timer0 has overflowed Signup and view all the answers

Which of the following correctly describes the T1RUN bit in the T1CON register?

It indicates if the Timer1 is actively running Signup and view all the answers

What is the effect of setting T1CKPS1:T1CKPS0 to binary 01 in the T1CON register?

Timer1 will have a prescale value of 1:2 Signup and view all the answers

When TMR1CS is set to 1, what does the T1SYNC bit control?

Synchronizes the external clock input Signup and view all the answers

What does the T1OSCEN bit control in the T1CON register?

The enablement of Timer1's oscillator Signup and view all the answers

What does setting the T0SE bit in the T0CON register do?

Selects Timer0 edge sensitivity for counting Signup and view all the answers

What does the RD16 bit in the T1CON register allow for Timer1?

To read/write the register as 16-bits Signup and view all the answers

Study Notes

Interrupts

An interrupt is a signal sent by peripherals/devices to the microprocessor for immediate attention
Interrupts cause the microprocessor to temporarily halt the execution of the current program and redirect its attention to a specific task
The task the microprocessor handles is called an Interrupt Service Routine (ISR)
Interrupts can be hardware or software-based.
- Hardware interrupts are initiated by other peripherals.
  - Non-maskable interrupts cannot be disabled.
  - Maskable interrupts can be disabled.
- Software interrupts are instructions that direct the processor during an unusual situation.
Benefits of using Interrupts
- Improved efficiency by handling multiple tasks simultaneously
- Real-time response to time-critical events
- Flexibility for implementing system functions such as input/output operations, error handling, and multitasking.

How the Processor Attends to An Interrupt

Once an interrupt process is enabled, the processor checks the interrupt request line or flag at the end of each instruction.
If an interrupt is present, the processor finishes executing its current instruction, saves the address of the next instruction into the stack, and goes to a special address called the interrupt vector.
The processor identifies the peripheral that caused the interrupt and executes the appropriate interrupt service routine, known as ISR.
When the ISR finishes, the last instruction should be "Return from Interrupt (RETFIE)" instead of a regular return instruction.
The "Return from Interrupt (RETFIE)" command pops the top of the stack, retrieves the address stored there, and the processor returns to where it was interrupted.
If multiple interrupt requests arrive at the same time, or a new interrupt request arrives while another ISR is being serviced, the processor uses a priority scheme to determine which interrupt request gets serviced first.

INTCON Register

The INTCON register is used to configure and track interrupt settings.
GIE/GIEH
- Global Interrupt Enable Bit
- When IPEN = 0:
  - 0 = Disables all interrupts
  - 1 = Enables all interrupts
- When IPEN = 1:
  - 0 = Disables all high priority interrupts
  - 1 = Enables all high priority interrupts
PEIE/GIEL
- Peripheral Interrupt Enable Bit
- When IPEN = 0:
  - 0 = Disables all peripheral interrupts
  - 1 = Enables all peripheral interrupts
- When IPEN = 1:
  - 0 = Disables all low priority interrupts
  - 1 = Enables all low priority interrupts
TMR0IE
- TIMER0 Overflow Interrupt Enable Bit
- 0 = Disables the TIMER0 overflow interrupt
- 1 = Enables the TIMER0 overflow interrupt
INT0IE
- INT0 External Interrupt Enable Bit
- 0 = Disables the INT0 external interrupt
- 1 = Enables the INT0 external interrupt
RBIE
- RB Port Change Interrupt Enable Bit
- 0 = Disables the RB port change interrupt
- 1 = Enables the RB port change interrupt
TMR0IF
- TIMER0 Overflow Interrupt Flag Bit
- 0 = TMR0 register did not overflow
- 1 = TMR0 register has overflowed (must be cleared in software)
INT0IF
- INT0 External Interrupt Flag Bit
- 0 = The INT0 external interrupt did not occur
- 1 = The INT0 external interrupt occurred (must be cleared in software)
RBIF
- RB Port Change Interrupt Flag Bit
- 0 = None of the RB7:RB4 pins have changed state
- 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

INTCON2 Register

INTEDG0
- INT 0 Edge Select Bit
- 0 = Interrupt on falling edge
- 1 = Interrupt on rising edge
INTEDG1
- INT 1 Edge Select Bit
- 0 = Interrupt on falling edge
- 1 = Interrupt on rising edge
INTEDG2
- INT 2 Edge Select Bit
- 0 = Interrupt on falling edge
- 1 = Interrupt on rising edge
TMR0IP
- TIMER0 Priority Bit
- 0 = Low Priority
- 1 = High Priority
RBIP
- PORTB Change Priority Bit
- 0 = Low Priority
- 1 = High Priority

INTCON3 Register

INT2IP
- INT 2 Priority Bit
- 0 = Low Priority
- 1 = High Priority
INT1IP
- INT 1 Priority Bit
- 0 = Low Priority
- 1 = High Priority
INT2IE
- INT 2 Enable Bit
- 0 = Interrupt Disable
- 1 = Interrupt Enable
INT1IE
- INT 1 Enable Bit
- 0 = Interrupt Disable
- 1 = Interrupt Enable
INT2IF
- INT 2 Flag Bit
- 0 = No Interrupt Occur
- 1 = Interrupt Occur
INT1IF
- INT 1 Flag Bit
- 0 = No Interrupt Occur
- 1 = Interrupt Occur

Interrupt Context Saving in PIC18

Instructions in an ISR can affect the contents of critical registers used in the main program.
This makes it necessary to save the contents of these registers at the start of the ISR and retrieve them before returning from the ISR.
In high priority interrupts, the contents of the W, BSR, and STATUS registers are automatically saved into their respective shadow registers.
The RETFIE FAST instruction retrieves the content of these registers at the end of the ISR.
Low priority interrupts do not automatically save the contents of these registers.

Interrupts on Digital Input

When PORTB pins in PIC18 microcontrollers are used as digital input lines, the following scenarios can trigger an interrupt:
- RB0/INT0, RB1/INT1, and RB2/INT2: Changes in logic level values on each line can be recognized to detect either rising or falling edges – triggered pulses.
- RB7:RB4: Changes in the collective logic level value on these lines can be recognized as interrupts.

What is a Timer?

A timer is a sequential counter that provides a precise counting interval to trigger an event.
The counting time is calculated by multiplying the count interval by the clock period.
When the counter expires (or overflows), an interrupt is raised.

Timer Types and Directions

Free-running timer: increments/decrements every clock interval.
Sequence controlled counter: increments/decrements every sequence event.
Up counter: Incremented at every clock pulse.
Down counter: Decremented at every clock pulse.

Timer Prescaler and Postscaler

A prescaler circuit is a counting circuit that reduces a high frequency signal to a low frequency using integer division to prolong the counting interval.
Prescaler circuits are connected before the actual timer circuit.
Postscaler circuits are connected after the actual timer circuit.

PIC18 Timers

Timer0
- 8/16 bit up counter
- Interrupt on overflow
- Selectable clock source
- Prescaler
Timer 1
- 16 bit up counter
- Interrupt on overflow
- Selectable clock source
- Prescaler
Timer 2
- 8 bit up counter with period comparators
- Prescaler and postscaler
- Interrupt on TMR2 to PR2 match
Timer 3
- Same functionality as Timer 1

T0CON Register

TMR0ON
- Timer0 On/Off Control bit
- 1 = Enables Timer0
- 0 = Stops Timer0
T08BIT
- Timer0 8-Bit/16-Bit Control bit
- 1 = Timer0 is configured as an 8-bit timer/counter
- 0 = Timer0 is configured as a 16-bit timer/counter
T0CS
- Timer0 Clock Source Select bit
- 1 = Transition on T0CKI pin
- 0 = Internal instruction cycle clock (CLKO)
T0SE
- Timer0 Source Edge Select bit
- 1 = Increment on high-to-low transition on T0CKI pin
- 0 = Increment on low-to-high transition on T0CKI pin
PSA
- Timer0 Prescaler Assignment bit
- 1 = TImer0 prescaler is NOT assigned.
- 0 = Timer0 prescaler is assigned.
T0PS2:T0PS0
- Timer0 Prescaler Select bits
- 111 = 1:256 Prescale value
- 110 = 1:128 Prescale value
- 101 = 1:64 Prescale value
- 100 = 1:32 Prescale value
- 011 = 1:16 Prescale value
- 010 = 1:8 Prescale value
- 001 = 1:4 Prescale value
- 000 = 1:2 Prescale value

Interrupt in Timer0

Flag bit: TMR0IF (bit 2 of the INTCON Register; 1 as interrupt on overflow)
Priority bit: TMR0IP (bit 2 of the INTCON2 Register; 1 as high priority)
Enable bit: TMR0IE (bit 5 of the INTCON Register; 1 as timer0 interrupt enable)

T1CON Register

RD16
- 16-Bit Read/Write Mode Enable bit
- 1 = Enables register read/write of Timer1 in one 16-bit operation
- 0 = Enables register read/write of Timer1 in two 8-bit operations
T1RUN
- Timer1 System Clock Status bit (READ-ONLY)
- 1 = Device clock is derived from Timer1 oscillator
- 0 = Device clock is derived from another source
T1CKPS1:T1CKPS0
- Timer1 Input Clock Prescale Select bits
- 11 = 1:8 Prescale value
- 10 = 1:4 Prescale value
- 01 = 1:2 Prescale value
- 00 = 1:1 Prescale value
T1OSCEN
- Timer1 Oscillator Enable bit
- 1 = Timer1 oscillator is enabled
- 0 = Timer1 oscillator is shut off
T1SYNC
- Timer1 External Clock Input Synchronization Select bit
- When TMR1CS = 1:
  - 1 = Do not synchronize external clock input
  - 0 = Synchronize external clock input
- When TMR1CS = 0:
  - This bit is ignored.
TMR1CS
- Timer1 Clock Source Select bit
- 1 = External clock (T1CKI pin)
- 0 = Internal instruction cycle clock (FOSC/4).
TMR1ON
- Timer1 On/Off Control bit
- 1 = Enables Timer1
- 0 = Stops Timer1

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Description

This quiz covers the concept of interrupts in microprocessors, detailing their types, benefits, and how the processor handles them. You'll learn about hardware and software interrupts, along with their impact on multitasking and system efficiency.