Overview of Interrupts in Microprocessors

Overview of Interrupts

• Interrupts are signals sent from external devices to the microprocessor to request the completion of a task.
• Interrupts are primarily used for data transfer between peripherals and the microprocessor.
• An interrupt is considered an emergency signal, and the microprocessor should respond as quickly as possible.
• When the microprocessor receives an interrupt, it suspends the currently executing program and branches to an Interrupt Service Routine (ISR) to handle the interrupt.
• ISRs are specific to each interrupt and allow the microprocessor to respond appropriately.
• Once the ISR is executed, the microprocessor returns to the main program using a RET instruction.

Types of Interrupts

• Hardware Interrupts: Generated by peripheral devices, also known as external interrupts.
• Software Interrupts: Internally generated within the microprocessor using software instructions, also known as internal interrupts.
• Maskable Interrupts: Can be delayed or rejected by the microprocessor.
• Non-Maskable Interrupts: Cannot be delayed or rejected by the microprocessor, used for emergency situations.
• Vectored Interrupts: The address of the ISR is fixed within the microprocessor, often used for specific tasks.
• Non-Vectored Interrupts: The address of the ISR is provided by the peripheral device, allowing for more flexible responses.

8085 Hardware Interrupts

• The 8085 microprocessor has five hardware interrupts:
  • TRAP
  • RST 5.5
  • RST 6.5
  • RST 7.5
  • INTR

8085 Software Interrupts

• Software interrupts are program instructions that, when executed, trigger an ISR.
• The 8085 microprocessor includes eight software interrupts:
  • RST 0
  • RST 1
  • RST 2
  • RST 3
  • RST 4
  • RST 5
  • RST 6
  • RST 7
• All software interrupts on the 8085 are vectored, cannot be masked, and cannot be disabled.

Maskable Interrupts

• Maskable interrupts can be enabled or disabled using software instructions.
• To mask interrupts, move the appropriate data to the accumulator and execute the SIM (Set Interrupt Mask) instruction.
• The RIM (Read Interrupt Mask) instruction allows reading the status of maskable interrupts into the accumulator.
• List of maskable interrupts: RST 7.5, RST 6.5, RST 5.5, INTR

Non-Maskable Interrupts

• Non-maskable interrupts are always enabled and cannot be disabled by software instructions.
• TRAP is a non-maskable interrupt.

Vectored Interrupts

• Vectored interrupts have a fixed memory location for transferring control from normal execution to the ISR.
• List of vectored interrupts:
  • RST 7.5
  • RST 6.5
  • RST 5.5
  • TRAP
• The addresses to which program control goes for vectored interrupts:
  • RST 7.5: 003C H (7.5 x 0008 H)
  • RST 6.5: 0034 H (6.5 x 0008 H)
  • RST 5.5: 002C H (5.5 x 0008 H)
  • TRAP: 0024 H (4.5 x 0008 H)

Non-Vectored Interrupts

• Non-vectored interrupts do not have a fixed memory location for transferring control from normal execution.
• The address of the memory location is sent along with the interrupt.
• INTR is a non-vectored interrupt.

Interrupt Priority

• The microprocessor can handle only one interrupt at a time.
• When multiple interrupts occur simultaneously, the microprocessor services them in order of priority.
• The highest priority interrupt is serviced first.
• In the 8085, TRAP has the highest priority, and INTR has the lowest priority.

TRAP

• A non-maskable interrupt, cannot be enabled or disabled.
• A vectored interrupt, with a vector address of 0024H.
• Has the highest priority.
• Level and edge-triggered: remains high from initiation until acknowledgment.
• Handles emergency situations like power failure, saving data from main memory to backup memory.

RST 7.5

• A maskable interrupt.
• A vectored interrupt with a vector address of 003CH.
• Second highest priority.
• Edge-triggered: goes high and doesn't need to stay high after acknowledgement.

RST 6.5

• A maskable interrupt.
• A vectored interrupt with a vector address of 0034H.
• Third highest priority.
• Level-triggered: stays high until acknowledged.

RST 5.5

• A maskable interrupt.
• A vectored interrupt with a vector address of 002CH.
• Fourth highest priority.

INTR

• A maskable interrupt.
• Non-vectored, with the address specified by the device.
• Lowest priority.

The 8085 Non-Vectored Interrupt Process

1. The interrupt process must be enabled using the EI instruction.
2. The 8085 checks for interrupts after executing every instruction.
3. If INTR is high, the 8085 completes the current instruction, disables interrupts, and sends an INTA (Interrupt Acknowledge) signal to the interrupting device.
4. INTA allows the I/O device to send an RST instruction through the data bus.
5. Upon receiving INTA, the 8085 saves the memory location of the next instruction on the stack and jumps to the ISR call location specified by the RST instruction.
6. The microprocessor executes the ISR.
7. The ISR should include an EI instruction to enable further interrupts within the program.
8. The RET instruction at the end of the ISR retrieves the return address from the stack, and the program returns to its interrupted state.

Interrupt Vector and the Vector Table

• An interrupt vector is a pointer to the location of the ISR in memory.
• All interrupts (vectored or otherwise) are mapped to a memory area called the Interrupt Vector Table (IVT).
• The IVT is located in memory page 00 (0000H - 00FFH).
• The IVT contains vectors that direct the microprocessor to the correct ISR when an interrupt occurs.
• Example: If a device interrupts the microprocessor using the RST 7.5 interrupt line, the microprocessor knows the ISR address location due to RST 7.5 being a vectored interrupt.
• The microprocessor will jump to the ISR location based on the vector address.

Summary of 8085 Interrupts

RST Instruction

• RST 0: 0000H

• RST 1: 0008H

• RST 2: 0010H

• RST 3: 0018H

• RST 4: 0020H

• RST 5: 0028H

• RST 6: 0030H

• RST 7: 0038H

• Software interrupts, vectored, maskable.

This quiz covers the fundamental concepts of interrupts in microprocessors, including their types and functions. Learn how interrupts facilitate communication between external devices and the microprocessor, and understand the role of Interrupt Service Routines (ISRs) in handling these signals. Test your knowledge on both hardware and software interrupts and their characteristics.