Embedded Interrupts PDF

INTERRUPT AND THE INTERRUPT SERVICE ROUTINE ENGR. KENN ARION WONG COMPUTER ENGINEERING DEPARTMENT WHAT is an INTERRUPT? It is a signal sent by peripherals/devices to get immediate attention of the microprocessor The processor temporarily halts the normal execution of a program and redirects...

INTERRUPT AND THE INTERRUPT SERVICE ROUTINE ENGR. KENN ARION WONG COMPUTER ENGINEERING DEPARTMENT WHAT is an INTERRUPT? It is a signal sent by peripherals/devices to get immediate attention of the microprocessor The processor temporarily halts the normal execution of a program and redirects processor’s attention to a specific task, service routine. Types of Interrupt Hardware interrupt – initiated by other peripherals. Non-Maskable interrupt – interrupts that cannot be disabled Maskable interrupt External peripheral sources Internal peripheral sources Software interrupt – instructions that directs the processor during an unusual situation. BENEFITS of using INTERRUPT Improved Efficiency: Interrupts allow the microprocessor to handle multiple tasks simultaneously without constantly polling for events. The processor temporarily halts the normal execution of a program and redirects processor’s attention to a specific task, service routine. Real-time Response: Interrupts enable the microprocessor to respond quickly to time-critical events. Flexibility: Interrupts can be used to implement various system functions, such as input/output operations, error handling, and multitasking. HOW DOES THE PROCESSOR ATTENDS AN INTERRUPT? When an interrupt process is enabled, it checks the interrupt request line or flag before the end of the execution of each instruction. If an interrupt is present, the processor completes the execution of the instruction, saves the address of the next instruction to the stack and directed to the special address called interrupt vector. The processor accepts the request and process a subroutine called Interrupt Service Routine (ISR). HOW DOES THE PROCESSOR ATTENDS AN INTERRUPT? The processor identifies the peripheral who raised the interrupt and executes the appropriate interrupt service routine. Once the processor completes the ISR, the last instruction should be “Return from Interrupt (RETFIE)” instead of Return instruction. Return from interrupt pops the top of the stack and retrieves the address and returns to continue the execution where it was interrupted. If multiple interrupt request arrive at the same time or an additional interrupt request arrives during the servicing of an interrupt, the priority scheme designed in the processor determines how these request are serviced. SERVICES that can TRIGGER an INTERRUPT Internal Timers Signal Processor Engines such as ADC and DAC Communication Services such Serial Comm, I2C and USB Digital Input Interrupts on selected PortB lines INTERRUPTS in PIC18 PIC18 family doesn’t have any non-maskable or software interrupts; all interrupts are maskable. The priority scheme is divided into 2 groups, high priority (0x0008) and low priority (0x0018). Any high priority interrupt can interrupt low priority interrupt. The processor checks 3 bits for each interrupt source before it raise an interrupt: Flag bit, Enable bit, and Priority Bit Interrupt flag bit is cleared manually after interrupt servicing. INTERRUPTS in PIC18 Interrupts are controlled by the following SFRs: RCON: Register Control INTCON: Interrupt Control INTCON2: Interrupt Control 2 INTCON3: Interrupt Control 3 PIR1 and PIR2: Peripheral Interrupt Request 1 & 2 PIE1 and PIE2: Peripheral Interrupt Enable 1 & 2 IPR1 and IPR2: Interrupt Priority Register 1 & 2 RCON REGISTER 7 6 5 4 3 2 1 0 IPEN - - - - - - - Interrupt Priority Enable 0 = Disable 1 = Enable Note: If priority is disabled, the priority bits are neglected and all interrupts branch to address 0x0008. INTCON REGISTER 7 6 5 4 3 2 1 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 7: GIE/GIEH: Global Interrupt Enable Bit When IPEN = 0: 0 = Disables all interrupts 1 = Enables all interrupts When IPEN = 1: 0 = Disables all high priority interrupts 1 = Enables all high priority interrupts 6: PEIE/GIEL: Peripheral Interrupt Enable Bit When IPEN = 0: 0 = Disables all peripheral interrupts 1 = Enables all peripheral interrupts When IPEN = 1: 0 = Disables all low priority interrupts 1 = Enables all low priority interrupts INTCON REGISTER 7 6 5 4 3 2 1 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 5: TMR0IE: TIMER0 Overflow Interrupt Enable Bit 0 = Disables the TIMER0 overflow interrupt 1 = Enables the TIMER0 overflow interrupt 4: INT0IE: INT0 External Interrupt Enable Bit 0 = Disables the INT0 external interrupt 1 = Enables the INT0 external interrupt 3: RBIE: RB Port Change Interrupt Enable Bit 0 = Disables the RB port change interrupt 1 = Enables the RB port change interrupt 2: TMR0IF: TIMER0 Overflow Interrupt Flag Bit 0 = TMR0 register did not overflow 1 = TMR0 register has overflowed (must be cleared in software) INTCON REGISTER 7 6 5 4 3 2 1 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 1: INT0IF: INT0 External Interrupt Flag Bit 0 = The INT0 external interrupt did not occur 1 = The INT0 external interrupt occurred (must be cleared in software) 0: RBIF: RB Port Change Interrupt Flag Bit 0 = None of the RB7:RB4 pins have changed state 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) INTCON2 REGISTER 7 6 5 4 3 2 1 0 - INTEDG0 INTEDG1 INTEDG2 - TMR0IP - RBIP TIMER0 PORTB Change Priority Bit INT 0, 1, 2 Edge Select Bit 0 = Interrupt on falling edge 1 = Interrupt on rising edge 0 = Low Priority 1 = High Priority INTCON3 REGISTER 7 6 5 4 3 2 1 0 INT2IP INT1IP - INT2IE INT1IE - INT2IF INT1IF INT 2 & 1 Priority Bit INT 2 & 1 Enable Bit INT 2 & 1 Flag Bit 0 = Low Priority 0 = Interrupt Disable 0 = No Interrupt Occur 1 = High Priority 1 = Interrupt Enable 1 = Interrupt Occur INTERRUPT CONTEXT SAVING in PIC18 The instruction in an ISR are likely affect the contents of the critical registers of the main program. Therefore, it is necessary to save the contents of these registers at the beginning of the ISR and retrieve those contents before returning from ISR. In high priority interrupts, the content of W, BSR and STATUS registers are automatically saved into their respective registers called shadow registers. The RETFIE FAST instruction retrieves the content of these registers at the end of the ISR. In low priority interrupts, the content of these registers are not automatically saved. INTERRUPTS on DIGITAL INPUT In PIC18 microcontrollers, when PORTB pins are used as digital input line, the following scenarios can trigger an interrupt: RB0/INT0, RB1/INT1, and RB2/INT2: Change of logic level value on each lines can be recognized to detect either rising edge or falling edge – triggered pulses. RB7:RB4: Change in collective logic level value on these lines can be recognized as interrupts. WHAT is a TIMER? A timer is a sequential counter that provides a precise counting interval to trigger an event The counting time is calculated by multiplying the count interval by the clock period That when the counter expires (or overflows), an interrupt will be raised TIMER TYPES and DIRECTION Free-running timer – timer that increments/decrements every clock interval Sequence controlled counter – timer that increments/decrements every sequence event Up counter: Incremented at every clock pulse Down counter: Decremented at every clock pulse TIMER PRESCALER and POSTSCALER A counting circuit that reduces a high frequency signal to a low frequency using integer division to prolong the counting interval Prescaler circuits are connected before the actual timer circuit Postscaler circuits are connected after the actual timer circuit TIMER PRESCALER and POSTSCALER How long does an 8bit counter will overflow using an 8Mhz clock source with the following prescaler and postscaler values? Without prescaler and postscaler With 1:16 prescaler; no postscaler With 1:8 prescaler; 1:4 postscaler PIC18 TIMERS Timer0: 8/16 bit up counter; interrupt on overflow; selectable clock source; prescaler Timer1: 16bit up counter; interrupt on overflow; selectable clock source; prescaler Timer2: 8bit up counter with period comparators; prescaler and postscaler; interrupt on TMR2 to PR2 match Timer3: Same with Timer1 TIMER0 as 8BIT UP COUNTER TIMER0 as 16BIT UP COUNTER T0CON REGISTER 7 6 5 4 3 2 1 0 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 7: TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 6: T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter 5: T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0CON REGISTER 7 6 5 4 3 2 1 0 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 4: T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin 3: PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. 0 = Timer0 prescaler is assigned. T0CON REGISTER 7 6 5 4 3 2 1 0 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 2 - 0: T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value INTERRUPT in TIMER0 Flag bit: TMR0IF (bit 2 of the INTCON Register; 1 as interrupt on overflow) Priority bit: TMR0IP (bit 2 of the INTCON2 Register; 1 as high priority) Enable bit: TMR0IE (bit 5 of the INTCON Register; 1 as timer0 interrupt enable) TIMER1 as 16BIT UP COUNTER T1CON REGISTER 7 6 5 4 3 2 1 0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 7: RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations 6: T1RUN: Timer1 System Clock Status bit (READ-ONLY) 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source T1CON REGISTER 7 6 5 4 3 2 1 0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value 3: T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off T1CON REGISTER 7 6 5 4 3 2 1 0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 2: T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock T1CON REGISTER 7 6 5 4 3 2 1 0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 INTERRUPT in TIMER1 Flag bit: TMR1IF (bit 0 of the PIR1; 1 as interrupt on overflow) Priority bit: TMR1IP (bit 0 of the IPR1; 1 as high priority) Enable bit: TMR1IE (bit 0 of the PIE1; 1 as interrupt enable) TIMER2 as 8BIT Period Timer T2CON REGISTER 7 6 5 4 3 2 1 0 - T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 7: Unimplemented 6-3: T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale … 1111 = 1:16 Postscale T2CON REGISTER 7 6 5 4 3 2 1 0 - T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 2: TMR2ON: Timer2 On bit 1 = Enables Timer2 0 = Stops Timer2 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1X = Prescaler is 16 INTERRUPT in TIMER2 Flag bit: TMR2IF (bit 1 of the PIR1; 1 as interrupt on TMR2 and PR2 match) Priority bit: TMR2IP (bit 1 of the IPR1; 1 as high priority) Enable bit: TMR2IE (bit 1 of the PIE1; 1 as interrupt enable)