Input-Output Organization

• Input-output organization covers topics like peripheral devices, I/O interface, asynchronous data transfer, transfer modes, priority interrupt, direct memory access (DMA), I/O processors, and serial communication.

Peripheral Devices

• Includes input devices like keyboards, optical input devices (card readers, paper tape readers, barcode readers, digitizers, optical mark readers), magnetic input devices (magnetic stripe readers), screen input devices (touch screens, light pens, mice), and analog input devices.
• Includes output devices like monitors (VDUs), card punchers, paper tape punchers, CRTs, printers (impact, ink jet, laser, dot matrix), plotters, analog devices, and voice output.

Input/Output Interface

• Provides a method for transferring information between internal computer storage and external I/O devices.
• Resolves differences between the computer and peripheral devices, which can include differing operational characteristics (electromechanical vs electronic), data transfer rates (slower peripherals vs faster CPU/memory), units of information (byte/block vs word), and data representations.

I/O Bus and Interface Modules

• Each peripheral has a corresponding interface module.
• The interface module decodes the device address and operation commands, provides signals to the peripheral controller, and synchronizes data flow, supervising the transfer rate between peripherals and the CPU or memory.
• A typical I/O instruction includes operation code, device address, and function code (command).

I/O Bus and Memory Bus

• The memory bus is for information transfers between the CPU and memory.
• The I/O bus is for information transfers between the CPU and I/O devices through their I/O interfaces.

I/O Interface

• Information in each port can be assigned a meaning, depending on the mode of operation.
  • Example: Port A = Data, Port B = Command, Port C = Status.
• The CPU initializes (loads) each port by transferring a byte to the Control Register, allowing it to define the mode of operation for each port.
• The programmable port enables changing the interface characteristics by modifying bits in the control register.

Asynchronous Data Transfer

• Involves the transfer of data between two independent units.
• Requires control signals to indicate the timing of data transmission between the communicating units.

Asynchronous Data Transfer Methods

• Strobe pulse: A strobe pulse is supplied to indicate when data transfer should occur.
• Handshaking: Data is accompanied by a control signal indicating data presence; the receiving unit responds with another control signal acknowledging receipt.

Strobe Control

• Employs a single control line to time each transfer.
• The strobe is activated by either the source or the destination unit.

Handshaking

• Solves the problem of source-initiated and destination-initiated transfers having no way of knowing whether data has been received/placed on the bus.
• Introduces a second control signal to provide a reply to the unit that initiates the transfer.

Source-Initiated Transfer Using Handshake

• Allows arbitrary delays from one state to the next.
• Permits each unit to respond at its own data transfer rate; the rate of transfer is determined by the slower unit.

Destination-Initiated Transfer Using Handshake

• Handshaking provides high flexibility and reliability, with successful completion relying on active participation by both units.
• If one unit is faulty, data transfer will not be completed, which can be detected by a timeout mechanism.

Asynchronous Serial Transmission

• Data transfer can occur in either serial or parallel fashion.
• In parallel data transmission, n bits of a message are transmitted through n separate conductor paths, enabling faster transfer but requiring more wires. This is suitable for short distances and high-speed applications.
• In serial transmission, each bit is sent sequentially, one at a time, requiring fewer wires but resulting in a slower transfer rate; it is less expensive.

Asynchronous Serial Transfer

• Each bit of the message is sent sequentially, and binary information is transferred only when available; the line remains idle when no information is transmitted.
• In this technique, each character consists of three points: Start, Stop and Character bits.
  • First bit, called start bit is always zero and is used to indicate the beginning character. -Last bit, called stop bit is always one and is used to indicate end of characters. -Bits in between the start and stop bits are known as character bits.

Asynchronous Serial Transfer

• Employs special bits inserted at each character code end: Start,Data and Stop bits.
• Receivers can determine a character base on 4 rules: the line must be in a 1-state (idle state), a transmission initiates with a start bit (0), follows character bits and ends with a stop bit with at least 1 bit time in a 1-state.

Universal Asynchronous Receiver-Transmitter (UART)

• Asynchronous interface used in IC (Integrated Circuits)
• Transmitter Register: Accepts data from the CPU through the data bus and transfers it to a shift register for serial transmission.
• Receiver: Receives serial information into another shift register before the complete data byte is sent to the receiver register.
• Status Register Bits: Used for I/O flags and for recording errors.
• Control Register Bits: Define baud rate, number of bits in each character, whether to generate and check parity, and the number of stop bits.

Modes of Transfer: Program-Controlled I/O

• There are 3 modes for data transfer: Program-Controlled I/O, Interrupt-Initiated I/O and Direct Memory Access.
• Program-Controlled I/O (Input Dev to CPU): Input Dev to CPU.
• Polling or Status Checking: When there is no data busy waiting in Loop happens, CPU involvement is continuous which makes CPU slowed down to I/O speed, it is simple and the hardware is least.

Interrupt-Initiated I/O

• When the I/O interface has the data transfer ready it sends an Interrupt Request to the computer.
• When the CPU has received the request it temporarly stops what it is doing and branches to a service program (ISR) to process the I/O transfer, then gets back to the original task.
• Interrupt-Driven I/O: Eliminates needless waiting but it passes everything through processor.

Priority Interrupt

• Determines which interrupt to serve first when two or more requests are done at the same time, it also determines which interrupts are allowed to interrupt the computer when one is already being serviced.
• Priority Interrupt by Software (Polling): When the order of devices is set (order of devices), Flexible and Low-cost, but Very slow.
• Priority Interrupt by Hardware: Needs a request manager to determine which has the highest priority request, it's Fast and its own service routine can be directly connected.

Hardware Priority Interrupt

• Daisy-Chain: Hardware with a Serial priority function to one Interrupt Request Line where CPU can respond and give the bus, however only one will get the request (the one close to the CPU).
• Parallel Priority Interrupt: with Interrupt and Mask Register based where the interrupt has different level and gets cleared by the program. When all of the mask has occurred, the Interrupt gets triggered and goes to de CPU where the bus can be loaded on the Priority Logic.

Interrupt Cycle

• At the end of each instruction, the CPU checks both IEN and IST, if IEN IST = 1, -> Interrupt Cycle
• Sequence to follow: decrement, push, transfer, disable.
• After each interrupt needs initial and final operations.

Interrupt Service Routine

• Must follow some intial and final steps in the interrupt system. -initial: clear mask, IST <- 0, save CPU contetns, IEN <- 1. -final: IEN <- 0, reset, clear reg, set mask and restore return address.

Direct Memory Access

• Is the block of data transfer from high speed devices (Drum, Disk, Tape). -With CPU initialized controller (DMA) sending memory address and its block size. Transfer happening directly between memory and the device withour the CPU need.
• CPU bus can be requested (BR) and granted (BG) with Read and Write. Controller also reads address, manages registers, requests the I/O Device.

DMA I/O Operation

• Needs instruction to set Address Register, Word Counter and Function. DMA performs I/O operations independently from CPU and with two main functions, input and output. -For the Input is set the read-signal, buffer the input, word assembly, Write-command, word count (WC) and interrupt when WC is 0.
  • Output goes through Address, Disassembly, Output is being buffered for all the bytes so CPU has not to interrupt until the word count is completed with 0 value.

DMA Transfer

• Acknowledges data interrupts between BG and BR, writing to Random Access memory through RD, WR , controller, address.

DAM Registers

• Address Register to mark start address (1000), register used for the word count and operation mode.
• Once all the data is transferred it will generate a CPU interrupt so it can all back control by setting the bus to 0.

DMA Modes

• Burst mode transfers all blocks in one burst.
• Stealing-cycle when transfers each word by stealing a cycle, making it always using the BR for all words with interrupt.

Cycle Stealing

• Stealing cycle operations: CPU accessing instructions and DMA controller access memory, to solve this access conflict there is a Memory Bus Controller with priority system and top spot given to DMA controller.
• CPU gets more memory than I/O and DMA controller. In this mode the CPU may have to remain idle if DMA controller causes memory cycles to take up more memory.

Input/Output Processor

• It has DMA capability and communicates with I/O, accesses cycles using memory.
• Consists or channel instructions which gives instructions and controls devices. CPU has to initiate for the channel to work independently.

Channel Communication

• While one has IOP operations the other has CPU instructions to check IOP or start I/O instruction if they are ok.

Serial Communication

• Data communication processor, modem, transmission and transfer modes. Simplex, Full and Half Duplex Character and Bit Oriented protocols.

Serial Communication : Data Communication Processor

• A specialised I/O that communicates with data networks and distributes data from terminals through the lines.

Serial Communication : Modem

• Stands for modulator/demodulator and devices can encode signals for transmission of information and decode the ones incoming.

Serial Communication : Modes of Transmission

• Simplex carries information that cannot indicated to other devices (radios).
• Half is capable of transmitting in both directions but only 1 at a time (walkie-talkie)
• Full can simultaneously transmit both (video/audio calls).

Serial Communication : Protocols

• They determine the order of devices calls. Protocols are a set of rules so devices don't cause errors.

Serial Communication : Protocols - Character oriented

• Its most binary code used is ASCII, it is mainly used in PPP.
• Code is for sync, headers, start/end bits and text.

Serial Communication : Protocols - Bit oriented

• It's independent of any code and less overhead than other types. Most are full-duplex and can be operated over 4 circuits.