Pipelined Memory Access Quiz and Flashcards: 5-Stage Pipeline Cycle

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Questions and Answers

What is the root cause of a data hazard in a pipeline?

Control hazard due to branches and jumps

Generalized forwarding of results to different functional units

Data dependency when the pipeline changes the order of read/write accesses to operands (correct)

Feedback loop between EX/MEM and MEM/WB pipeline registers

How is a data hazard typically resolved in a pipelined processor?

Forwarding results directly to the functional unit that requires it (correct)

Passing results only to ALU inputs

Preventing branches and jumps

Changing the order of instructions execution

What does a control hazard in a pipeline refer to?

Data dependency between read/write accesses in operands

Branches and jumps causing changes to the program counter (PC) (correct)

Generalized forwarding of results to different functional units

Feedback loop between pipeline registers

In the context of pipelining, what does 'branch hazard' refer to?

A branch may or may not change the program counter (PC) to other values Signup and view all the answers

How does generalized forwarding help mitigate data hazards in a pipelined processor?

Passing results directly to different functional units Signup and view all the answers

What is the essence of pipelining in CPU implementation?

To start executing one instruction before completing the previous one Signup and view all the answers

Which term refers to the time taken for an instruction to finish execution?

Latency Signup and view all the answers

What does PC-Relative Addressing in MIPS architecture involve?

The sum of the program counter and a constant in the instruction Signup and view all the answers

Which MIPS register is reserved for storing the return address?

$ra Signup and view all the answers

What is the purpose of the global pointer register in MIPS?

To point to a predefined location for global data access Signup and view all the answers

What does the term 'Throughput of a CPU' refer to?

The number of instructions completed per second Signup and view all the answers

What is the purpose of introducing pipeline registers between successive stages in a five-stage pipeline?

To store the results of a stage and use them as the input of the next stage Signup and view all the answers

Which type of hazard arises from resource conflicts such as a processor with 1 register write port but intending two writes in a clock cycle?

Structural hazard Signup and view all the answers

How does pipelining impact the average instruction time compared to unpipelined execution?

Reduces the average instruction time Signup and view all the answers

In a five-stage pipeline, what is done to eliminate conflicts between instruction fetch and data memory access?

Separate instruction and data memories Signup and view all the answers

Which type of hazard is caused by data dependencies that prevent the next instruction from executing in the designated clock cycle?

Data hazard Signup and view all the answers

What is the purpose of using the register file in two stages within a pipeline?

To write before read, allowing for faster processing Signup and view all the answers

Study Notes

Memory Access (MEM)

In load instructions, memory performs a read using the effective address.
In store instructions, memory writes data from the second register using the effective address.

Write Back (WB) Cycle

For Register-Register ALU or load instructions, write the result into the register file.
Results can come from memory (for load) or from the ALU (for ALU instructions).

Five-Stage Pipeline

Separate instruction and data memories to eliminate conflicts.
Use the register file in two stages, with half CC, in one clock cycle, write before read.
Introduce pipeline registers between successive stages to store results and use them as input for the next stage.

Speedup by Pipelining

Formula: Avg inst time unpipelined / Avg instr time pipelined.
Pipelining increases speed by allowing multiple instructions to be processed simultaneously.

Pipeline Hazards

Situations that prevent the next instruction from executing in the designated clock cycle.
Three classes of hazards: structural, data, and control hazards.

Structural Hazards

Root cause: resource conflicts.
Example: a processor with 1 reg write port but intends to perform two writes in a clock cycle.
Solution: stall one of the instructions until the required unit is available.

Data Hazards

Root cause: data dependency.
Problem: pipeline changes the order of read/write accesses to operands.
Solution: forwarding (directly feeding back results to the ALU inputs).

Control Hazards

Root cause: PC changes.
Example: branches and jumps (branch hazard).

Register Addressing

Indirect register addressing: load a value at a constant offset from the beginning of a structure.
PC-Relative Addressing: used for conditional branches, where the address is the sum of the program counter and a constant.

MIPS Registers

$zero: always 0.
$at: reserved for assembler.
$v0-$v1: stores results.
$a0-$a3: stores arguments.
$t0-$t7: temporaries, not saved.
$s0-$s7: contents saved for use later.
$t8-$t9: more temporaries, not saved.
$k0-$k1: reserved by operating system.
$gp: global pointer.
$sp: stack pointer.
$fp: frame pointer.
$ra: return address.

Pipelining Terminologies

Latency: the time for an instruction to complete.
Throughput of a CPU: the number of instructions completed per second.
Clock Cycle: everything in CPU moves in lockstep, synchronized by the clock.

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Description

Learn how the Five-Stage Pipeline works, including the Memory Access stage for loading and storing data, and the Write Back cycle for handling results from Register-Register ALU or load instructions. Understand the process of separate instruction and data memories to avoid conflicts for a single memory in instruction fetch.