DRAM: Understanding Computer Memory

DRAM: The Heart of Your Computer's Memory

• DRAM (Dynamic Random Access Memory) is your computer's main memory, where data is temporarily stored for fast access by the CPU.
• SSDs (Solid-State Drives) store data permanently, but data needs to be copied to DRAM for the CPU to use.
• DRAM is significantly faster than SSDs: Accessing SSD data takes about 50 microseconds, while DRAM access takes 17 nanoseconds (3,000 times faster).
• DRAM is limited by size and power consumption: While SSDs can hold terabytes of data, typical DRAM sticks hold gigabytes. DRAM also requires constant refreshed power for data retention.
• Prefetching is the process of moving data from SSD to DRAM before it's needed, improving performance and reducing loading times.

Inside a DRAM Stick and Chip

• DIMMs (Dual Inline Memory Modules): A DRAM stick with 8 chips, each of which has a 2D array of memory cells.
• Memory Channels: Connect the CPU to DRAM slots and provide data transfer paths. DDR5 channels transfer 32 bits at a time.
• Memory Controller: A component within the CPU that manages communication between SSDs, DRAM, and Cache memory.
• 2 Gigabytes DRAM Chip: Contains 8 bank groups, with 4 banks in each, for a total of 32 banks.
• Memory Cells: Each bank holds a massive array of 17 billion cells in 65,536 rows and 8,192 columns.
• Addressing: A 31-bit address is used to access a specific memory cell.
  • 3 bits select the bank group.
  • 2 bits select the bank.
  • 16 bits determine the row.
  • 10 bits are used for the column address.

Manufacturing DRAM

• Integrated Circuit (IC): Chips are fabricated on 300-millimeter Silicon wafers, producing 2,500 dies per wafer.
• Micron: A major DRAM manufacturer, producing both DRAM and SSDs under the brand name Crucial, which are often used in GPUs and other devices.

Inside a Memory Cell

• 1T1C Cell: A memory cell consisting of a capacitor and a transistor.
• Capacitor: Stores 1 bit of data as electrical charges.
• Transistor: Used to access and read/write data to the capacitor.
• Wordline: Connects to the transistor gate, turning it on for access.
• Bitline: Connects to the transistor channel, allowing data flow.
• Refresh Operation: Periodically recharges capacitors to prevent data loss due to charge leakage.

DRAM Array Organization

• Wordlines: Connect rows of transistors, enabling access to all transistors in a specific row.
• Bitlines: Connect columns of transistors, enabling reading or writing data.
• Row Decoder: Selects a single row for access.
• Column Multiplexer: Selects a specific group of 8 bitlines for access.
• Sense Amplifier: Amplifies small voltage changes on the bitlines to detect data.
• Read Driver: Reads 8 bits of data from a row and sends it to the CPU.
• Write Driver: Writes 8 bits of data to a row in the DRAM.

DRAM Data Transfer & Refresh

• Reading:
  • The CPU selects a specific bank, precharges all bitlines, and activates a row.
  • Capacitors in the open row perturb the bitlines based on their stored value.
  • Sense amplifiers amplify the voltage changes and drive bitlines to 1 or 0.
  • The column multiplexer selects the relevant 8 bitlines, which are transferred to the CPU by the read driver.
• Writing:
  • The CPU selects a specific bank, precharges all bitlines, and activates a row.
  • The CPU sends the data to be written to the write driver.
  • The write driver overrides the previous bitline voltages and writes the new data to the capacitors.
• Refresh:
  • All rows are sequentially closed, bitlines are precharged, and then a row is opened.
  • Sense amplifiers recharge the capacitors in the open row.
  • This refresh process happens once every 64 milliseconds per bank.

Importance of DRAM

• DRAM enables incredibly fast data access for the CPU, making modern computing possible.
• Without DRAM, tasks like playing video games would be significantly slower.
• Different types of DRAM are optimized for different devices, like GPUs (VRAM) and smartphones.

Conclusion

• DRAM is a complex technology, but understanding its key principles helps appreciate the fundamental workings of your computer.
• The speed and accessibility of DRAM make it the foundation of modern computing.

DRAM Memory Banks

• Banks of memory cells handle up to 4,800,000,000 read and write requests per second, while refreshing every memory cell in a bank row by row around 16 times a second.
• Opening a single row within a bank requires a series of steps, including precharging, row activation, and column selection.
• Opening an already open row, called a row hit or page hit, is significantly faster than a row miss, as specific steps are bypassed.
• DDR5 DRAM has 32 banks, allowing for independent operation of each bank's rows, columns, sense amplifiers, and row decoders.
• Multiple rows can be open simultaneously, increasing the likelihood of a row hit and reducing data access time.
• CPU memory controller, programs, and compilers are optimized for increasing row hits.
• Thrashing, frequently switching between rows, is inefficient.
• Banks are significantly taller than wide, resulting in a chip that is 65,000 rows tall by 262,000 columns wide.
• The 31 divisions between columns create banks, increasing flexibility and efficiency in reading, writing, and refreshing.

Burst Buffer and Burst Length

• A burst buffer is a 128-bit temporary storage location that temporarily caches data for faster access.
• The 10-bit column address is split into 6 bits for the multiplexer and 4 bits for the burst buffer.
• The burst buffer allows for simultaneous access to 128 memory cells, effectively caching data for quick retrieval using the 4-bit buffer address.
• By cycling through the 4 bits, 16 sets of 8 bits (a burst length of 16) can be read quickly.
• The burst buffer provides granularity, allowing access to any set of 8 bits even if the data requests jump around.

Sub-Arrays and Sense Amplifiers

• The massive array of memory cells is divided into smaller blocks (1,024 by 1,024), called sub-arrays.
• Sub-arrays have intermediate sense amplifiers below them, subdividing wordlines and bitlines.
• Subdividing bitlines reduces the distance and amount of wire that each memory cell is connected to, reducing capacitor size.
• Subdividing wordlines decreases capacitive load, reducing the time required to turn on all access transistors in a row.

Folded DRAM Architecture and Sense Amplifier

• The folded DRAM architecture uses two bitlines per column, alternating rows of memory cells connected to the left and right bitlines.
• When one row is active, half the bitlines are active, and the other half are passive, and vice-versa for the next row.
• The sense amplifier uses a cross-coupled inverter, amplifying the signal from the active bitline and inverting it for the passive bitline.
• This creates a differential pair, where bitlines are always oppositely charged, providing noise immunity and reducing parasitic capacitance.

Benefits of Differential Pair

• During precharge, the cross-coupled inverters are disconnected, allowing charge to flow between the bitlines, resulting in an average of 0.5 volts.
• Noise immunity is increased as the oppositely charged bitlines create electric fields that counter external noise.
• Reduced parasitic capacitance allows for better signal amplification.

SDRAM and DDR

• SDRAM (Synchronous Dynamic Random Access Memory) and DDR (Double Data Rate) relate to the timing of addresses, command signals, and data.
• These topics were omitted to keep the video focused on core DRAM concepts.

Future of Engineering Education

• The video emphasizes the importance of engineering education for the future.
• The video is supported by Patreon and YouTube Memberships to fund their educational content.
• The video acknowledges the contributions of doctoral students from the Florida Institute for Cybersecurity Research in reviewing its content.

Explore the fundamentals of Dynamic Random Access Memory (DRAM) and its crucial role in your computer's performance. This quiz covers topics such as DRAM's speed compared to SSDs, its architecture, and the process of prefetching. Test your knowledge about how DRAM influences data access and system efficiency.