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Questions and Answers
Which of the following components is NOT a part of a processor?
Which of the following components is NOT a part of a processor?
What is the total number of instruction types in the CS147DV instruction set?
What is the total number of instruction types in the CS147DV instruction set?
What does the acronym CPU stand for?
What does the acronym CPU stand for?
Which memory model addressability does the CS147DV instruction set utilize?
Which memory model addressability does the CS147DV instruction set utilize?
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What is the maximum byte addressable memory capacity for a 32-bit processor?
What is the maximum byte addressable memory capacity for a 32-bit processor?
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What is the minimum number of electrical lines connected into the processor chip on the motherboard as per the schematic?
What is the minimum number of electrical lines connected into the processor chip on the motherboard as per the schematic?
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Memory can initiate data transactions to the processor.
Memory can initiate data transactions to the processor.
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What architecture uses separate memory for data and instructions?
What architecture uses separate memory for data and instructions?
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The base of a number system is defined as the ______ used to represent values.
The base of a number system is defined as the ______ used to represent values.
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What is the corresponding hexadecimal representation for the binary value 1011001010₂?
What is the corresponding hexadecimal representation for the binary value 1011001010₂?
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How many values can a Boolean variable have?
How many values can a Boolean variable have?
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Match the following identities with their respective rules:
Match the following identities with their respective rules:
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A truth table is an alternate representation of a Boolean expression.
A truth table is an alternate representation of a Boolean expression.
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Which of the following performance metrics is represented by MIPS?
Which of the following performance metrics is represented by MIPS?
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An equal length instruction characteristic is beneficial for pipelined architecture.
An equal length instruction characteristic is beneficial for pipelined architecture.
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What does CPI stand for?
What does CPI stand for?
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When a program accesses a memory location, it is likely to access the same location again in the near future. This property is known as ______.
When a program accesses a memory location, it is likely to access the same location again in the near future. This property is known as ______.
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Match the following performance measurement metrics with their definitions:
Match the following performance measurement metrics with their definitions:
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What type of data hazard occurs when the next instruction address depends on the prior instruction's result?
What type of data hazard occurs when the next instruction address depends on the prior instruction's result?
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What upper limit for speedup can be expected from a sixteen-stage pipelined processor compared to a non-pipelined processor?
What upper limit for speedup can be expected from a sixteen-stage pipelined processor compared to a non-pipelined processor?
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Data forwarding is performed statically before program execution.
Data forwarding is performed statically before program execution.
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A ______ storage device needs to go through every data until the desired data is reached.
A ______ storage device needs to go through every data until the desired data is reached.
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Which cache write strategy updates all the subsequent memory hierarchies when data is written in the cache?
Which cache write strategy updates all the subsequent memory hierarchies when data is written in the cache?
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Which two stages are involved in a control hazard situation?
Which two stages are involved in a control hazard situation?
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If there are 50 misses out of 1000 cache memory accesses, what is the hit rate?
If there are 50 misses out of 1000 cache memory accesses, what is the hit rate?
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The cache line index for a block address of 29 with 8 cache lines is ______.
The cache line index for a block address of 29 with 8 cache lines is ______.
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Access time in storage systems is referred to as latency.
Access time in storage systems is referred to as latency.
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Which type of data hazard resolution measure is performed dynamically during program execution?
Which type of data hazard resolution measure is performed dynamically during program execution?
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What kind of cache mapping allows any reference address to be mapped to any cache line?
What kind of cache mapping allows any reference address to be mapped to any cache line?
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A superscalar processor has a performance improvement based on its ability to execute multiple instructions simultaneously.
A superscalar processor has a performance improvement based on its ability to execute multiple instructions simultaneously.
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What is the total number of ALUs in a superscalar processor with a 5x performance improvement?
What is the total number of ALUs in a superscalar processor with a 5x performance improvement?
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The area of memory where virtual memory addresses are mapped to physical memory addresses is managed by the ______.
The area of memory where virtual memory addresses are mapped to physical memory addresses is managed by the ______.
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Match the following types of computing systems with their definitions:
Match the following types of computing systems with their definitions:
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What classification applies to a processor that uses multiple ALUs?
What classification applies to a processor that uses multiple ALUs?
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Memory performance improvements are unnecessary if processor speed is increased.
Memory performance improvements are unnecessary if processor speed is increased.
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What is the page offset size in bits for a page size of 1KB?
What is the page offset size in bits for a page size of 1KB?
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How can a modern multi-core laptop be classified in terms of computing architecture?
How can a modern multi-core laptop be classified in terms of computing architecture?
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Solid state disks (SSDs) enhance system performance by reducing page fault penalties.
Solid state disks (SSDs) enhance system performance by reducing page fault penalties.
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The part of the disk that implements virtual memory is known as ______ space.
The part of the disk that implements virtual memory is known as ______ space.
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What type of cache is transformed from a direct mapped cache with 16 lines into 4-way set associative?
What type of cache is transformed from a direct mapped cache with 16 lines into 4-way set associative?
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In Amdahl's law, if 60% of a system can be improved by 6 times, what is the overall speedup?
In Amdahl's law, if 60% of a system can be improved by 6 times, what is the overall speedup?
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Which operation is said to be performed in SIMD architecture?
Which operation is said to be performed in SIMD architecture?
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In a Boolean function F(a,b,c,d), minterms 4, 5, 6 can be grouped as prime implicant.
In a Boolean function F(a,b,c,d), minterms 4, 5, 6 can be grouped as prime implicant.
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In a Boolean function F(a,b,c,d), minterms 0, 2, 8, 10 can be grouped as prime implicant.
In a Boolean function F(a,b,c,d), minterms 0, 2, 8, 10 can be grouped as prime implicant.
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In K-map, row and column indices are encoded using:
In K-map, row and column indices are encoded using:
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What is the full form of SOP?
What is the full form of SOP?
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A 32-bit ripple carry adder contains ___ half adders.
A 32-bit ripple carry adder contains ___ half adders.
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Which logic gate is used to build an overflow detection circuit for a binary ripple carry addition/subtraction circuit?
Which logic gate is used to build an overflow detection circuit for a binary ripple carry addition/subtraction circuit?
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In general division algorithm, in which direction is the quotient shifted?
In general division algorithm, in which direction is the quotient shifted?
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What should be the expected value of the overflow bit if an addition computes the correct result?
What should be the expected value of the overflow bit if an addition computes the correct result?
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Which feature is needed for a 32-bit unsigned divider to manipulate the divisor?
Which feature is needed for a 32-bit unsigned divider to manipulate the divisor?
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Match the addressing modes with their descriptions:
Match the addressing modes with their descriptions:
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In little endian strategy, the higher byte is stored in the lower memory address.
In little endian strategy, the higher byte is stored in the lower memory address.
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How many rows and columns are there in the K-map for a function F(W,X,Y,Z)?
How many rows and columns are there in the K-map for a function F(W,X,Y,Z)?
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Which register feature is needed for a 32-bit unsigned multiplier, which stores/manipulates multiplicand?
Which register feature is needed for a 32-bit unsigned multiplier, which stores/manipulates multiplicand?
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If COn is the carry out bit from the n-th 1-bit full adder, which bits should be combined for overflow detection?
If COn is the carry out bit from the n-th 1-bit full adder, which bits should be combined for overflow detection?
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Study Notes
Processor Components
- A processor comprises a controller, ALU (Arithmetic Logic Unit), and a register file.
- Memory is external to the processor.
- A processor with two 32-bit buses (address and data) and one control signal (RnW) will have a minimum of 65 electrical lines connected to the motherboard.
- The processor initiates data transactions with memory; memory is a passive device.
CS147DV Instruction Set
- The CS147DV instruction set has three types of instructions: R, I, and J.
CPU Definition
- CPU stands for Central Processing Unit.
CS147DV Memory Model
- The memory model in the CS147DV instruction set is word addressable.
32-bit Processor Memory Capacity
- A 32-bit processor can address 232 bytes of memory.
- This equates to 4 gigabytes (GB) of memory.
- Harvard architecture uses separate memory for data and instructions.
- Von Neumann architecture uses a single memory space for both.
Number Systems
- The base of a number system is the number of symbols used to represent values.
Boolean Logic
- A Boolean variable can have two values: 0 or 1.
- A truth table represents a Boolean function.
- Boolean identities include the commutative (X + Y = Y + X, X * Y = Y * X), associative (X(YZ) = (XY)Z), distributive (X + YZ = (X + Y)(X + Z) and De Morgan's ((X + Y)' = X'Y'), laws.
- Dual functions have AND/OR swapped; variables remain unchanged.
- Neighboring cells in a K-map are used for prime implicants (groups of 2, 4, 8 etc).
- K-maps use gray codes for indexing rows and columns.
- A minterm is a product of variables, where each variable appears either in its complemented or uncomplemented form.
Logic Circuit Design
- SOP stands for sum of products.
- A 4-variable K-map has 4 rows and 4 columns.
- Overflow detection in a binary ripple carry adder/subtractor uses an XOR between the carry-out bit (Cn) and the second-to-last carry-out bit (Cn-1).
- A binary ripple carry adder that implements subtraction (A - B) for a 32-bit signed integer requires a NOT gate for the subtrahend and an additional operation (+B').
- Overflow is 0 if the result is correctly computed during addition.
- Multiplicand's register in unsigned multiplication uses parallel load.
- Multiplier's register in unsigned multiplication is shifted right in the general algorithm.
- The general division algorithm shifts the quotient left.
- Quotient's register in unsigned division uses parallel load.
- Data storage elements, memory, I/O devices, and operation codes are part of ISA.
- Little-endian stores the higher byte at a lower memory address; Big-endian does the opposite.
- Processor architecture depends on the set of supported instructions and data storage characteristics.
- Response time is the time between task start and completion.
- Throughput is the total task amount accomplished within a given time.
- MIPS (Million Instructions Per Second) measures throughput.
- CPI is cycles per instruction.
- Instruction counts depend on the programming language, algorithm, ISA, and compiler.
- Response time is the average completion time of benchmark programs.
- Control hazards happen when next instruction addresses depend on a previous one's result.
- Pipeline stages should use independent resources.
- The maximum speedup for a 16-stage pipeline is 16 (compared to non-pipelined version).
- Static hazards (instruction reordering) happen before execution; dynamic hazards (stalling, data forwarding) happen during execution.
- Dynamic probabilistic branch prediction works well for programs with many loops.
- Control hazards arise from conditional branch instructions (bne, beq, jal, j).
- Sequential storage needs to scan all data to reach desired data.
- Random access storage directly accesses data at its location.
- Programs often access the same memory locations repeatedly (temporal locality).
- Programs often access memory locations close to existing ones (spatial locality).
- Cache hit rate + miss rate = 1.
- Access time (latency) is the time needed to access a storage system.
- Cache line index = (block address) mod (# of cache lines).
- Write-through caches update all memory hierarchies with new cache data.
- Write-back caches have a more complicated control circuit.
- A 5x improvement in a superscalar processor suggests 5 ALUs running in parallel.
- Register file sizes in KB unit for 32-bit processor with 8 strands will be 1KB
- GPUs are SIMD computing systems.
- A system with multiple ALUs are vector systems.
- Modern laptops are MIMD systems.
- Using Amdahl's law, system speedup can be calculated.
- SMP (symmetric multiprocessor) systems share a common memory.
- A full associative cache can map a reference address to any cache line.
- A direct-mapped cache with 1K lines converted to fully associated cache will have 1 set.
- A direct-mapped cache with 16 lines converted to 4-way set associative will have 4 sets.
- Memory performance improvement is important as processor speeds increase.
- Pages contain equal number of cache blocks.
- Virtual memory mappings are stored in main memory and the TLB.
- SSDs improve system performance by reducing page fault penalties.
- Space needed to maintain virtual memory on a disk is known as swap space.
- Paging size is calculated as log base 2 of the page size.
- A processor issues virtual memory address, not a real memory device address, in a virtual memory system.
- K-maps use Gray codes. Prime implicants can be built using don't cares. K-map technique works for 2 to 4 variables. Not all prime implicants are needed. Don't cares are used to generate the minimum SOP form.
- NOR and NAND gates are universal logic gates.
- CMOS technology primarily uses NAND and NOR gates.
- Combination logic design steps include initial specification, truth table generation, Boolean function optimization, mapping, and verification.
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Description
This quiz covers the key components of the CS147DV processor, including the controller, ALU, and memory model. It also addresses the instruction set types and the memory addressing capabilities of a 32-bit processor. Test your knowledge on the essentials of CPU architecture and instruction sets!
