CPU Instruction Execution Cycle

Instruction Execution Cycle

• It is a sequential process where a CPU fetches, decodes, and executes instructions, also accessing memory.

Key Phases of Instruction execution

• Instruction Fetch (IF) points to the memory address of the next instruction.
• Instruction Decode (ID) converts the instruction into an understandable format.
• Operand Fetch (OF) extracts operands from registers or memory. (This step is optional)
• Execution (EX) is when the Arithmetic Logic Unit (ALU) performs calculations or logical operations.
• Write-Back (WB) is where data is transferred between the CPU and memory.

Performance Metrics

CPI (Cycles Per Instruction)

• Indicates the average number of clock cycles a processor needs to execute a single instruction
• CPI = Total Number of Cycles / Total Instructions Executed and works as a Key Performance Indicator

MIPS (Million Instructions Per Second)

• Measures the execution speed of a computer's CPU.
• MIPS = Instruction Count / Execution Time X 10^6
• Affected by factors such as clock speed, Instruction Set Architecture (ISA), and pipeline efficiency.

FLOPS (Floating Point Operations Per Second)

• Measures the number of floating-point operations a CPU can perform in one second.
• Types of FLOPS include single-precision (FP32), double-precision (FP64), and half-precision (FP16).
• FLOPS = Number of Cores x Clock Speed (Hz) x FLOPS per Cycle
• Is affected by factors like CPU architecture, clock speed, and the number of cores.

CPU Architectures

General Information

• Defines how a processor processes instructions. The two main types are RISC and CISC.

RISC (Reduced Instruction Set Computer)

• Uses simple and uniform instruction formats, with each instruction taking one clock cycle to execute.
• Focuses on load/store architecture, where memory operations are separate from ALU operations.
• Adheres to key principles like simplicity, uniform instruction format, and register-based operations.
• Advantages of RISC include faster execution speed, simpler hardware design, and energy efficiency.
• Disadvantages of RISC include requiring more RAM/memory and more work for the compiler.

CISC (Complex Instruction Set Computer)

• Designed to execute a large number of complex instructions using multi-step operations or address modes.
• Key principles of CISC include a rich instruction set, multi-cycle execution, and memory-based operations.
• Advantages of CISC include reduced code size, ease of programming, and efficient use of memory.
• Disadvantages of CISC include higher power consumption, slower clock speeds, and complexity in design.

Addressing Modes

• Defines how the CPU identifies the operands for an instruction
• Immediate Addressing: This mode is fast since no memory lookup is required
• Register Addressing: The operand is stored in a CPU register.
• Direct Addressing: Requires a single memory access to fetch the operand.
• Indirect Addressing: The instruction provides an address that contains the actual memory address of the operand.
• Indexed Addressing: The operand address is calculated by adding an index value to a base address.
• Relative Addressing: The operand address is calculated relative to the current value of the program counter (PC).
• Base-Register Addressing: Uses a base register to hold the base address.
• Stack Addressing: The operand is automatically taken from the top of the stack (Last In, First Out – LIFO).

Topic 2: Number Systems

• It is a way of representing and organizing numbers using specific symbols or digits.
• Binary Number System uses digits 0 and 1
• Octal Number System uses base 8, using digits 0 to 7
• Hexadecimal Number System uses digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and letters A, B, C, D, E, F
• Unsigned Binary Numbers represent only magnitude and not the sign.
• Signed Binary Numbers use a fixed number of bits to represent a range of numbers that include negative and positive values.

IEEE 754

• It is the standard used for floating-point arithmetic in computers
  • Single Precision (32-bit)
  • Double Precision (64-bit)
  • Extended Precision (128-bit)

Arithmetic Operations

• Binary Addition
• Binary Subtraction
• Binary Multiplication
• Binary Division

Topic 3: CPU

• The core of any computing system -The instruction cycle includes Fetch, Decode, Execute, and Write-Back.

Single-Cycle Processor

• Executes each instruction in exactly one clock cycle

Use cases

• Simple Embedded systems
• Basic Microcontrollers
• Low-power applications

Multi-Cycle Processor

• Designed by dividing instruction execution into multiple cycles.

Use cases

• General purpose processors
• Systems requiring power efficiency.

Pipelined Processor

• Allows overlapping instruction execution through multiple stages. The 5 stages are Instruction Fetch, Instruction Decode, Execution, Memory Access, and Write-Back.
• Pipeline Hazards:
  • Structural Hazards: Multiple instructions need the same resource, and hardware resources are insufficient to support all.
  • Data Hazards: Instructions close together depend on the same data. There are 3 main types: RAW (Read After Write), WAR (Write After Read), and WAW (Write After Write).
  • Control Hazards: The next instruction is uncertain, arising from the pipelining of branches and other instructions.

Use cases

• Modern Desktops
• Mobile Processors
• High-Performance Computing Apps

Forwarding (Data Forwarding)

• Technique used in computer architecture to reduce delays
  • Reduces pipeline stalls, increases the efficiency of CPU, and enhances performance.
  • It requires additional hardware and cannot resolve all types of hazards.

Brand Prediction

• This is a technique used to guess the outcome of a decision Types:
  • Static Prediction: Does not learn from past behavior
  • Dynamic Prediction: Analyzes previous branch results
• Handling Wrong Prediction: Speculative Execution, Pipeline Flushing, Branch Target Buffer

Modern CPUs and Security Risks

• Advanced Branch Prediction:
  • AGE (Tagged Geometric Predictor): Highly accurate branch predictor
  • Neural Network Predictors: Uses AI-like methods

Security Risks

• Spectre Attack: Tricks the CPU into leaking sensitive data
  • Mitigation: CPU Manufacturers have added security patches

SUPERSCALAR and OUT OF ORDER EXECUTION

• Superscalar Execution: Allows CPU to execute multiple instructions in parallel. Its key features include multiple pipelines, parallel instruction processing, and efficient resource utilization.
  • Advantages: Higher Throughput and Efficient Use of Execution Units
  • Disadvantages: Complex Scheduling Logic and Wasted Execution Units
• Out of Order Execution: Enables the processor to execute instruction when required resources are available. -Dynamic Scheduling, Dependency Resolution, and Reordering Buffer.
  • Disadvantages: Increased Hardware Complexity and Higher Power Consumption

Real World Applications

• Modern CPUs
• Gaming & High Perf Computing
• AI & Machine Learning

Topic 4: Primary Memory

• Type of computer memory that is directly accessible by the CPU.
  • Its role in computer systems includes storing active data, enhancing system performance, and executing programs.

Types of Primary Memory

• Random Access Memory (RAM): type of volatile computer memory that temporarily stores data. Characteristics include being High Speed, Volatile Memory, and having Temporary Storage.
  • Types of Random Access Memory: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM)
• Read - Only Memory (ROM): type of non-volatile memory used in computers. Characteristics include being Non-Volatile, Pre-Programmed, and having Permanent Data Storage.
  • Types of Read - Only Memory: Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM)

Cache Memory

• Acts as a buffer to speed up CPU operations Levels:
  • L1
  • L2
  • L3

Mapping Techniques

• Direct Mapping: Each RAM block maps to exactly one cache line.
• Associative Mapping: Any RAM block can be placed in any cache line.
• Set-Associative Mapping a cache memory technique that combines direct mapping and fully associative mapping

Write Policies

• Determine how data is updated between the cache and main memory
• Write-Through Policy same data is also written to main memory
• Write-Back Policy is first written to cache and only updated in main memory when necessary
• Write Allocation determines whether data is loaded into the cache when written to memory
  • Write-allocate: Data is first loaded into the cache
  • No-write allocate data is written directly to memory

Virtual Memory

• Memory management technique to compensate for physical memory shortages
• Enables efficient execution of large programs that exceed available RAM
  • Concept abstracts physical memory, allowing programs to operate
  • Mechanism Memory Mapping, Page Swapping, and Address Translation
  • Paging memory management scheme that divides both virtual and physical memory
  • Page Tables data structure that maps virtual page numbers
  • Page Frames Fixed-size blocks in physical memory where pages are stored

Secondary Storage

• Non-volatile memory used to store data long-term
  • Types of Secondary Storage: Hard Disk Drive and Solid State Drive

Solid State Drive

• Type of nonvolatile storage device that uses flash memory to store data
  • Function: Data Writing (unlike HDDs) and Data Reading (the controller retrieves)
• Data Erasing Flash memory cells must be erased
• Wear Leveling to prevent certain blocks

Redundant Array of Independent Disks

• Used to combine multiple physical hard drives into one logical unit. Function: Data Redundancy, Improved Performance, Increased Storage Capacity.
  • There are multiple types of RAID including RAID 0 (Stripping), RAID 1 (Mirroring), RAID 5, RAID 6 (Striping with Double Parity), RAID 10 (1+0, Mirroring and Striping) RAID 50 and RAID 60

Memory Access Method

• Techniques used to read and write data in memory and are crucial for optimizing data retrieval speeds
• There are multiple types of memory access method
  • Sequential Access process of obtaining data one piece at a time
  • Direct Access allowing data to be retrieved directly from its unique address
  • Random Access temporarily stores instructions that are actively being used or processed - Examples are DDR4, DDR3, LPDDR4, SRAM AND DRAM
  • Associative Access way of finding data based on its content, not its location - Examples are Hardward Security, Cache Memory and search engines

Abbreviations

• List of abbreviations and meanings provided in the document
  • IF - Instruction Fetch
  • ID - Instruction Decode
  • OF - Operand Fetch
  • EX - Execution
  • MEM – Memory Access
  • WB - Write-Back
  • CPI - Cycles Per Instruction
  • MIPS – Million Instructions Per Second
  • FLOPS – Floating Point Operations Per Second
  • FP16 – Half-Precision Floating Point (16-bit)
  • FP32 - Single-Precision Floating Point (32-bit)
  • FP64 - Double-Precision Floating Point (64-bit)
  • RISC - Reduced Instruction Set Computer
  • CISC - Complex Instruction Set Computer
  • PC - Program Counter
  • DRAM - Dynamic Random Access Memory
  • SRAM - Static Random Access Memory
  • ROM - Read-Only Memory
  • PROM - Programmable Read-Only Memory
  • EPROM - Erasable Programmable Read-Only Memory
  • EEPROM - Electrically Erasable Programmable Read-Only Memory
  • RAM - Random Access Memory
  • HDD - Hard Disk Drive
  • SSD - Solid State Drive
  • RAID - Redundant Array of Independent Disks
  • RAID 0 - Striping
  • RAID 1 - Mirroring
  • RAID 5 - Striping with Parity
  • RAID 6 – Striping with Double Parity
  • RAID 10 - Mirroring + Striping
  • RAID 50 – Multiple RAID 5 Arrays
  • RAID 60 – Multiple RAID 6 Arrays
  • IEEE 754 – Standard for Floating-Point Arithmetic
  • DDR – Double Data Rate
  • LPDDR - Low Power Double Data Rate
  • RAW - Read After Write (Data Hazard)
  • WAR – Write After Read (Data Hazard)
  • WAW – Write After Write (Data Hazard)
  • AGE - Tagged Geometric Predictor (Advanced Branch Prediction)
  • L1 / L2 / L3 - Cache Levels