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Questions and Answers
What is the purpose of dividing a 16-bit address into tag bits, block bits, and word bits in a direct-mapped cache?
What is the main function of a dirty bit in the cache memory?
What does the write-through protocol involve when updating data in the cache?
What is the fundamental idea behind pipelining a CPU?
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In a pipelined CPU, what can cause instruction hazards?
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How many clock cycles are typically required to execute each instruction in a 4-stage execution model without using a pipeline?
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What is the primary purpose of overlapping execution stages in pipelining?
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What does it mean when the address in the PC is sent to memory to 'fetch' the instruction to be executed?
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When can the address in the PC be incremented by the CPU?
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In the simple accumulator machine, what do the three most significant bits of a one-byte instruction represent?
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What function does the ALU perform in the simple accumulator machine?
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How are MAR, MDR, and the read enable line used to read data from memory in the simple accumulator machine?
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How many clock cycles does each instruction require in the simple accumulator machine?
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Why does the simple accumulator machine only allow sequential execution of instructions?
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How does the use of a cache improve performance in a computer system?
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What is typically the size relationship between CPU caches and main memory/RAM?
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What is one significant reason why a cache is faster than accessing data from main memory?
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What can be deduced given that there are no branch/jump instructions in the simple accumulator machine?
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