Computer Architecture Slide Set A-7 Quiz

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What is the purpose of dividing a 16-bit address into tag bits, block bits, and word bits in a direct-mapped cache?

To identify which cache block a memory block should be placed in (correct)

To indicate the number of words in a cache block

To determine the size of cache blocks

To differentiate between read and write operations

What is the main function of a dirty bit in the cache memory?

To manage the cache replacement policy

To indicate whether a cache block has been modified (correct)

To determine the number of cache misses

To track the number of cache hits

What does the write-through protocol involve when updating data in the cache?

Data is never written to main memory

Data is written to both the cache and main memory simultaneously (correct)

Data is updated in the cache after being updated in main memory

Data is only written to the cache

What is the fundamental idea behind pipelining a CPU?

Overlapping stages of execution to improve throughput Signup and view all the answers

In a pipelined CPU, what can cause instruction hazards?

Data dependencies Signup and view all the answers

How many clock cycles are typically required to execute each instruction in a 4-stage execution model without using a pipeline?

$4$ clock cycles per instruction Signup and view all the answers

What is the primary purpose of overlapping execution stages in pipelining?

To increase overall throughput. Signup and view all the answers

What does it mean when the address in the PC is sent to memory to 'fetch' the instruction to be executed?

Reading the instruction by the memory and sending it back to the CPU Signup and view all the answers

When can the address in the PC be incremented by the CPU?

After it is sent to the memory Signup and view all the answers

In the simple accumulator machine, what do the three most significant bits of a one-byte instruction represent?

3-bit opcode for instruction Signup and view all the answers

What function does the ALU perform in the simple accumulator machine?

Arithmetic and logic operations on data Signup and view all the answers

How are MAR, MDR, and the read enable line used to read data from memory in the simple accumulator machine?

MAR specifies memory address, MDR holds retrieved data, read enable line initiates data transfer Signup and view all the answers

How many clock cycles does each instruction require in the simple accumulator machine?

Two clock cycles per instruction Signup and view all the answers

Why does the simple accumulator machine only allow sequential execution of instructions?

'Call' and 'return' instructions are not supported Signup and view all the answers

How does the use of a cache improve performance in a computer system?

By storing frequently used data/instructions closer to the CPU for faster access Signup and view all the answers

What is typically the size relationship between CPU caches and main memory/RAM?

CPU caches are typically less than 0.1% of main memory/RAM Signup and view all the answers

What is one significant reason why a cache is faster than accessing data from main memory?

Main memory is physically farther from the CPU than cache is Signup and view all the answers

What can be deduced given that there are no branch/jump instructions in the simple accumulator machine?

Sequential execution is enforced as instructions can't be altered mid-program Signup and view all the answers

Computer Architecture Slide Set A-7 Quiz

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