Computer Architecture: Pipelining & ILP

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Questions and Answers

What is the primary benefit of pipelining in processors?

Reduced power consumption

Increased clock speed

Increased instruction throughput (correct)

Simplified hardware design

Which of the following is NOT a phase in a typical 5-stage pipeline?

Memory Access (MEM)

Data Processing (DP) (correct)

Execution (EX)

Instruction Fetch (IF)

What is a common solution to data hazards in pipelining?

Increasing cache size

Forwarding (correct)

Adding more clock cycles

Using larger instruction sets

Superscalar processors can execute how many instructions per clock cycle?

More than one instruction Signup and view all the answers

Which of the following best describes Instruction-Level Parallelism (ILP)?

Parallel execution of multiple instructions Signup and view all the answers

Control hazards in pipelining are primarily caused by what type of instructions?

Branch instructions Signup and view all the answers

What technique is used to handle control hazards in pipelining?

Branch prediction Signup and view all the answers

Which of the following is considered a limitation of Instruction-Level Parallelism (ILP)?

Dependencies between instructions Signup and view all the answers

Which cache miss occurs when data accessed is not present in the cache, regardless of its access history?

Compulsory Miss Signup and view all the answers

What is the primary goal of prefetching in cache optimization?

To minimize cache misses Signup and view all the answers

In a write-back cache policy, what happens when a cache block is evicted?

The data is written to main memory only if it has been modified Signup and view all the answers

What is the main purpose of branch prediction in computer architecture?

To reduce control hazards in instruction pipelines Signup and view all the answers

Which of these is NOT a type of branch prediction technique?

Selective Prediction Signup and view all the answers

Which model of parallelism involves processes communicating via message passing?

Distributed Memory Signup and view all the answers

What is a key challenge associated with parallel computing?

Ensuring efficient synchronization and load balancing between processors Signup and view all the answers

What is NOT a characteristic of multi-core architecture?

Exclusive access to resources by each core Signup and view all the answers

Study Notes

Pipeline

Pipelining overlaps instruction execution, boosting throughput without higher clock speeds.
Divides instruction execution into stages (fetch, decode, execute, memory access, write-back).
A typical 5-stage pipeline includes instruction fetch, decode, execution, memory access, and write-back.
Advantages include increased throughput and efficient resource usage.
Hazards include structural (hardware limitations), data (instruction dependencies), and control (branching).
Solutions for hazards involve forwarding, stalls, reordering, branch prediction, delayed branching, or pipeline flushing.

ILP (Instruction-Level Parallelism) & Superscalar

ILP is the potential for multiple concurrent instruction execution.
Exploits parallelism within code for performance enhancement.
Techniques include pipelining, superscalar execution (multiple parallel functional units), out-of-order execution (instruction reordering for maximum utilization), and speculative execution (executing instructions before confirmation).
Superscalar processors dispatch multiple instructions per clock cycle using multiple pipelines or functional units.
Key features include parallel instruction dispatch, dynamic instruction scheduling, and dependency checking to avert hazards.
Limitations involve instruction dependencies, branch instructions, and resource constraints.

Cache Optimization

Cache is a fast, small memory near the processor to accelerate access to frequently used data.
Cache hierarchies (L1, L2, L3) reduce latency by progressively placing caches closer to the processor.
Associativity (direct-mapped, set-associative, fully-associative) balances speed and hit rate.
Write policies (write-through, write-back) manage data updates to memory.
Prefetching fetches data before required based on access patterns.
Block size affects performance; larger blocks improve spatial locality but increase miss penalties.
Replacement policies (LRU, random, FIFO) handle cache block eviction.
Cache miss types include compulsory miss (first access), conflict miss (block conflicts in certain cache organizations), and capacity miss (working data set exceeds cache size).

Branch Prediction

Branch prediction anticipates branch outcomes (e.g., if/else, loops) optimizing processor flow.
Techniques include static prediction (always predict taken or not taken) and dynamic prediction (uses past outcomes).
Dynamic predictors include 1-bit predictors (simple, based on last outcome) and 2-bit predictors (prevents frequent changes in prediction).
Branch target buffers store branch addresses for faster execution.
Global history registers observe recent branch decisions to predict patterns better.
Speculative execution executes instructions based on prediction; incorrect prediction causes pipeline flushing.

Parallel Computing

Parallel computing employs multiple processors or threads to simultaneously execute parts of a task.
Parallelism types include data parallelism (same operation on separate data elements) and task parallelism (separating tasks among processors).
Parallelism models include shared memory (all processors share access) and distributed memory (processors have their individual memories, relying on message passing).
Challenges include load balancing, data synchronization, and communication overhead.

Multi-Core Architecture

Multi-core processors feature multiple independent processing units (cores) on a single chip, improving efficiency and performance.
Key aspects include shared resources (caches, memory controllers, buses shared between cores) and communication mechanisms (shared memory or message passing).
Multi-core processors reduce power consumption by lowering clock speeds, thus reducing heat output.
Multi-core architectures prove suitable for multi-threaded applications and virtualization.

Verilog

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Description

This quiz explores the concepts of pipelining and instruction-level parallelism (ILP) within computer architecture. You'll learn about the stages of instruction execution, the advantages of pipelining, and the types of hazards that can occur. Additionally, it covers superscalar execution and various techniques to enhance performance.