Computer Architecture: Pipelining

A situation where two instructions require the same hardware resource at the same time.

A situation where an instruction depends on the result of a previous instruction that's still being processed.

A situation where an instruction alters the flow of execution, affecting which instruction comes next.

The process of pausing the pipeline execution to resolve a hazard.

A solution to hazards where only the affected instruction stalls, allowing others to proceed.

A measure of how many clock cycles are needed to execute an instruction.

The logic that detects and resolves hazards in a pipeline.

A technique where instructions are executed in a series of stages, overlapping execution for speed.

A stalling mechanism used to prevent a pipeline stage from accessing data that is not yet available. It introduces a 'bubble' or delay in the pipeline.

A period of inactivity in a pipeline stage, usually introduced due to a stall. It represents a wasted clock cycle.

Instructions are fetched and executed in a sequential order, without any overlap.

Instructions are broken down into smaller stages and overlap in execution, leading to faster processing speeds.

A type of hazard that occurs when an instruction tries to access the result of a previous instruction that has not yet been calculated.

A type of hazard that occurs when an instruction needs to access a specific resource (e.g., a functional unit) that is already being used by another instruction.

Forwarding is a technique used to resolve data hazards by providing the result of a previous instruction to the next instruction that needs it, even if the first instruction hasn't finished writing its result to memory or registers.

Forwarding occurs when a previous instruction's result is made available to the next instruction's ALU (Arithmetic Logic Unit) in the pipeline, even though the previous instruction hasn't reached the writeback (WB) stage.

A load instruction that directly writes the result of a previous instruction into a register, without going through the memory writeback stage.

A type of data hazard where the previous instruction is a load instruction that hasn't finished reading data from memory.

Even with forwarding, data hazards can still occur in some cases, especially in scenarios involving memory load instructions.

The stage in the pipeline where an instruction reads data from memory.

The stage in the pipeline where an instruction writes its result to memory or registers.

RAW (Read After Write) hazard occurs when an instruction tries to read a register before the previous instruction has finished writing to it.

A common solution for dealing with RAW hazards is forwarding or bypassing. This means the result of the previous instruction is directly forwarded to the next instruction without waiting for it to be written back to the register file.

A WAR (Write After Read) hazard occurs when an instruction attempts to write to a register before the previous instruction has finished reading it.

A WAW (Write After Write) hazard occurs when an instruction attempts to write to a register before the previous instruction has finished writing to it.

The MIPS 5-stage pipeline design doesn't allow for data hazards. This is because every instruction takes 5 stages to complete, and the write-back stage (stage 5) is responsible for updating the register file.

In more complex pipeline designs, data hazards, especially WAR and WAW can become more prominent.

The simplest method to address RAW hazards is to stall the pipeline. This involves temporarily halting the pipeline execution to wait for the previous instruction to finish writing the data.

A technique for resolving control hazards by prefetching the instructions at the target address of a branch instruction, in parallel with the execution of current instructions. This allows the pipeline to continue execution without stalling, as the target instructions are already ready.

A dedicated memory resource for storing recently fetched instructions, especially useful for loops and jumps. This speeds up execution by reducing the need to access the main memory repeatedly.

A method for handling control hazards where the branch instruction is delayed by one or more cycles, allowing the pipeline to execute the next instruction as if the branch was not taken. This simplifies pipeline control and improves performance in some cases.

A pipeline design where multiple pipelines are used to handle different branches concurrently. Each pipeline prefetches the instructions for its corresponding branch, allowing for efficient execution on multiple paths.

A technique for handling control hazards by predicting the outcome of a branch instruction before it is actually executed. The pipeline continues execution based on the prediction, and if incorrect, it adjusts the pipeline state to catch up.

A stall is a delay introduced in the instruction pipeline to resolve a data hazard. It ensures that the instructions are executed in the correct order and data dependencies are respected.

A control hazard is a delay introduced during a branch instruction due to uncertainty about the next instruction to be executed.

The number of clock cycles it takes to complete a task or instruction in a pipeline, taking into account hazards and stalls.

A pipeline is a technique used to improve the performance of a processor by overlapping the execution of multiple instructions.