Computer Architecture Overview

Computer Architecture

• Architecture vs. Organization: Architecture refers to the programmer-visible attributes (instruction set, data representation, I/O mechanisms, addressing techniques). Organization details how the features are implemented (control signals, interfaces, memory technology). Examples include whether there's a multiply instruction or if it's done through repeated addition.

Structure and Function

• Structure: Describes how components relate to each other.
• Function: Explains the operation of individual components as part of the overall structure.

Functional View

• Computer functions: Data processing, data storage, data movement, and control are all necessary.
• The diagram shows the interconnectedness of components, such as data processing facility, data storage facility, and control mechanism.

Operations

• Data Movement: The computer must facilitate data transfer between itself and the outside world.
• Storage: Temporary data storage is crucial for the computer to process data.
• Processing from/to storage: Data can be processed after being moved from storage or to an I/O unit. This can include calculations, data transformations, or other manipulations.
• Processing from storage to I/O: The data often takes different forms and the processing requirements may vary.

The Computer - Top Level Structure

• Components: CPU, main memory, and I/O are interconnected by system bus.
• Internal bus: Connects internal components within the CPU.

The Processor

• Purpose: Fetch and execute instructions.
• Components: Arithmetic Logic Unit (ALU), Control Unit, and specialized registers (e.g., PC, MAR, MDR, ACC).

Von Neumann Machines

• Definition: An example architecture and organization of modern computers.
• Stored-program concept: Data and instructions are stored in the same memory space.

Von Neumann Machines (Cont.)

• Stored program concepts: Instructions and data are stored in the main memory.
• Arithmetic logic unit (ALU): This unit carries out arithmetic and logical operations.
• Control unit: Interprets the instructions and executes the actions.
• Input/Output (I/O) equipment: Operated by the control unit.
• Example: The IAS computer.

Computer Registers

• Definition: Storage in the CPU.
• Types of registers: Memory Buffer Register (MBR), Memory Address Register (MAR), Instruction Register, Instruction Buffer Register, Program Counter (PC), Accumulator (ACC).

IBM Systems

• History: IBM was a major manufacturer of punched-card processing equipment, leading to stored-program computers (e.g., 701, 702).
• Impact: These models paved the way for later IBM systems.

Transistors

• Development: Replaced vacuum tubes, contributing to smaller, cheaper, and less energy-consuming devices.
• Significance: Mark a major advancement in electronics and computer technology. (Second generation machines).

Semiconductor Memory

• Evolution: From magnetic core memory to semiconductor memory, increasing capacity and speed.
• Capacity increase: Capacity doubles roughly every year for semiconductor memory.

Evolution of Intel Microprocessors

• 4004 and 8008: Milestone processors, representing significant progress in integrated circuit technology.

Evolution of Intel Microprocessors (Cont.)

• 8080: A 8-bit microprocessor, important for its general-purpose architecture.
• 8086: A 16-bit microprocessor, representing a significant increase in processing power over its predecessor.
• 80386: Important 32-bit microprocessor.

Speeding it up

• Techniques for improvement in computational speed, including branch prediction and data flow analysis.
• Branch prediction: Predicts the next instruction sequence to optimize processing.
• Data flow analysis: Optimizes instruction scheduling by analyzing dependencies between instructions.

What is a Program?

• Definition: A sequence of steps involving arithmetic or logical operations.
• Control signals: Different signals are needed for each step.

Function of Control Unit

• Unique codes: Each operation has a unique code (like "ADD," "MOVE").
• Control signals: Hardware segments process codes, generating control signals for each operation.

Instruction Cycle

• Two steps: Fetch and execute cycles.

Fetch Cycle

• Program Counter (PC): Holds the address of the next instruction to fetch.
• Memory location: Instruction is fetched from the pointed memory location.
• Instruction Register (IR): The instruction is loaded in the IR.
• Processor action: Instruction is interpreted and required actions are performed.

Execute Cycle

• Processor-memory: Data transfer between the processor and memory happens.
• Processor I/O: Data exchange between the processor and input/output modules happens.
• Data processing: Arithmetic and/or logical operations.
• Control: Modifying the execution sequence.

Interrupts

• Mechanism: Allows other modules to interrupt the normal flow of processing.
• Sources: Can originate from programs, timers, input/output, or hardware failures.
• Cycle: Process interrupt, suspend current program, then store context, then set PC accordingly, and continue.

Connecting

• Interconnections: All components in the system need to be connected via an interconnection network.
• Different types of units: Different units, like Memory, Input/Output, and CPU need different types of connections.

Memory Connection

• Receive signals: Receives address and control signals to read or write.
• Send data: Sends data in response to read/write requests.
• Timing: Includes timing signals involved in the operation.

Input/Output Connection

• Similar to Memory: Interconnected to the CPU via the system bus.
• Control signals: Used to control the operation of peripherals.
• Addresses: Used to identify specific devices.

CPU Connection

• Reads and Writes: Data reads from/writes to memory locations.
• Control signals: Used for communication with memory/I/O devices.
• Interrupts: Handles interrupts.

Buses

• Types of Buses: Control, Address, and Data Buses.

What is a Bus?

• Definition: A communication pathway that connects two or more devices.
• Broadcast: A single signal usually relayed to many destinations.
• Channels: Multiple channels are possible for separate functions on a single bus.
• Power lines: Can be absent and their presence not shown.

Data Bus

• Data transfer: Specifically for transferring data in a computer system.
• Instructions vs data: Functionally interchangable (instructions are just data).
• Determines performance: The width of the data bus is key to the performance.

Address Bus

• Source/Destination: Used to specify memory locations or I/O devices.
• Memory capacity: Its width determines the maximum number of addressable units.
• Example: CPU access a location in memory, sending the address via the address bus.

Control Bus

• Control signals: Convey instructions/requests/commands.
• Examples: Memory read/write, interrupt requests, and clock signals.

Memory Hierarchy

• Registers: Built directly into CPU.
• Main memory: Fast storage that the CPU can read and writes.
• Cache memory: Faster than main memory to hold data and instructions frequently used.
• External memory/Backing store: Additional storage for large quantities of data not actively used.

Memory Hierarchy - Diagram

• Diagram shows the layout of memory components in a hierarchy.

Performance

• Access Time: Between address request and valid data retrieval.
• Cycle time: Time needed for the memory to recover before the next access.
• Transfer rate: Data transfer rate from memory.

Access Methods

• Sequential: Data access is in a linear order from a defined point.
• Direct: Data access based on a unique address and then a sequential search.
• Random: Data access independently of the previous locations.
• Associative: Data access is through a comparison with contents in a specific portion of the memory.

Internal Memory

• Definition: Random Access Memory (RAM), volatile (lost when power is off).
• Types: Dynamic RAM (DRAM) and Static RAM (SRAM).
• DRAM: Holds data as electric charge in capacitors, requiring refreshing.
• SRAM: Storing data as on/off switches, no need for refreshing.

Internal Memory (Cont.)

• Read Only Memory (ROM): Non-volatile memory for permanent storage of data and instructions, like microprogramming and function tables.

Location and Capacity

• Location: Inside the CPU or external to the CPU.
• Capacity: Word size, fundamental part of organization, and the number of words or bytes.

Unit of Transfer

• Internal: Usually controlled by the data bus width.
• External: Larger units like blocks.
• Addressable units: Smallest address assigned in memory.

Cache

• Function: High-speed storage between main memory and processor.
• Location: Usually on or close to the processor.

Cache/Main Memory Structure

• Illustrates how cache and main memory are connected and structured for data access.

Cache Operation – Overview

• CPU request: When CPU needs data from memory, accessing starts in the cache.
• Cache check: CPU checks if the required data resides in cache.
• Fetching from cache: Data is quickly retrieved from cache.
• Fetching from main memory: If data isn't in cache, then data and instruction block is retrieved from main memory, loading into cache.

Cache Operation – Flowchart

• Graphical representation of the steps involved in accessing/transferring data between cache and CPU/main memory.

Cache Addressing

• Mapping and Addressing: The logic for mapping virtual/physical addresses in caches.
• Virtual to physical address: Translation performed generally in a hardware unit (MMU).

Mapping Function

• Fully Associative: Memory block can be loaded into any cache line.
• Set Associative: Memory block allocation in sets allowing for more than one place to store a memory block.
• Direct Mapping: Each block maps to a single cache line.

Fully Associative Mapping (Example)

• Description: Example computation of block size, cache size, number of lines.
• Calculations: Detail the computation and rationale of parameters involved in a fully associative mapping scenario.

Fully Associative Mapping Summary

• Address length: (s + w) bits.
• Addressable units: 2^(s+w) words or bytes.
• Block Size/Line Size: 2^w words or bytes.
• Blocks in Main Memory: 2^S
• Cache Lines: Undetermined, depending on the design.
• Tag size: (s-d) bits.

Set Associative Mapping

• Sets: Cache divided into sets.
• Line Mapping: A block maps to any line in a given set.
• Way Associative: Describes mapping of blocks among cache lines.

Set Associative Mapping (Example)

• Block Size, Cache Size, Main Memory parameters: Example calculation, similar to fully associative mapping.
• Set Number: The set number part of the mapping algorithm.

Set Associative Mapping Summary

• Address length: (s + w) bits.
• Addressable Units: 2^(s + w) words or bytes.
• Block Size/Line Size: 2^w words or bytes.
• Blocks in Main memory: 2^s
• Number of sets: 2^d
• Lines in cache: kv= k*2^d
• Tag size: (s – d) bits. (For each set)

Direct Mapping

• Mapping: 1 block in main memory maps to a single unique line in the cache.
• Address Parts: Address divided into parts: Least significant bits identify word, most significant bits indicate memory location.
• Tag Bits: Identify the cache line corresponding to a particular memory block.

Direct Mapping (Example)

• Block size: 4 bytes
• Cache size: 16k (2^14) lines of 4 bytes
• Main memory size: 16MB (2^24 bytes)
• Address Details: 24-bit address, (2^24 = 16M)
• Set Number/Tag size computations: Calculation to determine the set number, tag size and other necessary details for memory mapping.

Direct Mapping Summary

• Address length: (s + w) bits.
• Addressable units: 2^ (s + w) words or bytes.
• Block size/line size: 2^w words or bytes.
• Blocks in Main memory: 2^s
• Lines in Cache: m = 2^r
• Tag size: (s – r) bits.

Replacement Algorithms/Direct Mapping

• Replacement policy: In a direct mapping system each block maps to a single line.
• Replace strategy: If a line contains a requested block and a new block needs to be accessed, then replace the old block on the line.

Replacement Algorithms/Associative & Set Associative Mapping

• Hardware algorithm: Least Recently Used (LRU), First-In First-Out (FIFO), Least Frequently Used (LFU), and Random replacement policies.

Write Policy

• Write through: Updates made to both cache and main memory simultaneously.
• Write back: Updates made only to the cache initially; written to main memory only when the block is to be replaced.

Unified VS. Split Caches

• Unified cache: Single cache for both data and instruction.
• Split cache: Separate caches for data and instruction.
• Advantages of unified/split: Performance/hit rates may improve when using separate caches with specialized functions compared to unified.

Virtual Memory

• Definition: Technique for extending physical memory by using secondary storage space (e.g., hard disk) as an extension.
• Purpose: Provides access to a larger memory space than physically available in RAM.

Virtual Address

• Virtual addresses: Addresses used by the processor.
• Physical address: Addresses that the system uses to access physical memory locations.
• Translation: Translation between physical and virtual address is crucial to allow virtual memory to function.
• Memory Management Unit (MMU): Translates virtual addresses to physical addresses.

Page

• Definition: Collection of memory words.
• Page fault: Required page is not in physical memory therefore it needs swapping.
• Demand paging: The OS brings in pages as needed.
• Virtual address to physical mapping: Through page table and possibly a translation lookaside buffer (TLB).

Page Table

• Definition: A table in the main memory used to map virtual addresses to physical addresses.
• Control bits: Maintain status information about each page (e.g., valid, dirty).

Translation Lookaside Buffer (TLB)

• Purpose: Cache for page table entries for faster virtual-to-physical address translation.
• Structure similarity: Similar to ordinary memory cache.

TLB Operation

• Flowchart depicting the steps involved in a TLB access.

Input/Output Problems

• Peripherals and communication: Peripherals such as screens, printers, and modems can have varied speeds, data sizes and data formats. Need specialized modules to handle the speed, variety, and amount of data from these devices.
• Slower transfer: Input/Output transfer rates are generally slower than CPU and RAM.
• I/O Modules: Needed to handle the variety and handling differences in rates.

Input/Output Module

• Functions: Management of interfaces to the CPU and memory, as well as specific interfaces for different peripherals (including control signals and addresses).
• Examples: Management of transfers, control over peripherals, and error detection/correction.

External Devices

• Categories of external devices: Human-readable devices, machine-readable devices, and communication devices.
• Examples: Printers, monitors, modem, and network cards.

I/O Module Function

• Modules: Control, timing, communications with the CPU, managing data transfers for I/O devices, and error checks.

I/O Steps

• CPU checks status: To determine if an I/O module is ready or contains the needed data, the CPU will check the status of the module.
• Status return: The response from the I/O module in terms of status.
• Data transfer: Data is then sent or received as required.

Input/Output Techniques

• Programmed I/O: CPU directly controls the data transfer.
• Interrupt-driven I/O: I/O module signals the CPU when it's ready to transfer or receive data.
• Direct Memory Access (DMA): Special hardware takes over data transfer, freeing up the CPU.

Programmed I/O

• CPU control: The CPU has direct control of the I/O transfer by continuously monitoring/checking the I/O status.
• Status monitoring: The CPU repeatedly monitors/checks the status of the I/O device to check when a device is ready.
• Command and data: Command or data can be sent to/from the I/O device after checking status.
• Time wasted: The CPU spends time constantly checking the status.

Interrupt-driven I/O

• No waiting: CPU doesn't have to repeatedly monitor I/O device status for completion.
• Interrupt signal: The I/O module sends an interrupt signal when data is ready.
• Improved efficiency: The CPU is freed from continuously checking I/O status.

Direct Memory Access (DMA)

• Hardware control: DMA controller transfers data between I/O device and main memory without continual CPU intervention.
• Improved performance: DMA speeds up data transfer significantly because it alleviates CPU interaction for simpler transfers.

CPU Structure

• Fetch Instructions: The CPU fetches instructions from memory.
• Interpret Instructions: The CPU interprets the meaning of fetched instructions and necessary actions.
• Fetch Data: The CPU retrieves data from memory based on the instructions.
• Process Data: The CPU manipulates/modifies data based on the instructions.
• Write Data: Results from the data processing is written back to either memory or other parts of the system.

Data Flow (Instruction Fetch)

• Fetch (general): The Program Counter (PC) holds the next instruction's address. The CPU sends the address in the PC to MAR, which sends the address to the memory to retrieve the instruction (read).
• Memory read: Control unit requests memory read.
• Instruction Register (IR): Instruction loaded to instruction register (IR).
• Program Counter (PC): Incremented generally after each instruction.

Data Flow (Data Fetch)

• Examined instruction (IR): The instruction in the instruction register (IR) is examined.
• Addressing (indirect): An indirect addressing cycle may be performed where the CPU reads the right most bits of the MBR (memory buffers register) and copies to MAR.
• Control unit requests read: Control sends request to memory unit for a read.
• Operand address to MBR: The operand address is stored to the MBR (memory buffer register).

Data Flow (Execute)

• The CPU executes instructions, which may involve various functions (memory reads, writes, data processing).

Data Flow (Interrupt)

• The CPU must handle/respond as needed.
• Saving the current state or context includes saving the Program Counter (PC) value, saving relevant register states, and saving memory contents.
• A special memory location (often a stack pointer/register), typically saved to the MAR, receives content copied from the MBR.

Prefetch

• Fetch instruction: Fetching instructions from memory.
• Fetch access time: Accessing and fetching instructions are separated from the current instruction execution.
• Instruction instruction: Instructions executed.

Improved Performance

• Fetch shorter: Prefetching can make fetch component time faster.
• Additional stages: Increasing stages often improves performance/execution time.

Pipelining

• Overlap stages: Multiple stages of an instruction's execution are overlapped, enabling concurrent execution, improving CPU throughput.
• Stages: Stages in the process include instruction fetch, decode, operands calculation, operand fetch, execute, write results.

Timing Diagram for Instruction Pipeline Operation

• Diagram showing the timing for each step/instruction (i.e. instruction fetch, decode, calculate operands, fetch operands, execute instruction and write result).

Six-Stage CPU Instruction Pipeline

• Diagram showing the steps (stages) involved in a six-stage CPU instruction pipeline.

Pipeline Hazards

• Resource hazard: Conflicts can happen if stages try to use the same resource simultaneously in the pipeline.
• Data hazard: Data dependency problems can happen if an instruction depends on the results of previously executed instructions.
• Control hazard: Branch/jump instructions can create pipeline problems if a wrong path is followed.

Resource Hazards

• Multiple resources (e.g. multiple memory accesses): Situations where instructions/stages in pipeline need the same resources (e.g. main memory) simultaneously.
• Serial execution: Serial execution occurs when a particular instruction cannot be completed unless preceding ones are finished.

Data Hazards

• Conflicting operand access: If instructions are out of sequence, then the operand values may change in unpredictable ways.
• Data dependency: An instruction needs the result of a previous instruction, otherwise problems may occur/
• Pipeline stall: In a pipeline, if there is a data dependence, it will need to stall before the current instruction can execute.

Control Hazards

• Branch prediction: Problems arise when the pipeline incorrectly predicts the branching path.
• Incorrect sequence: Instructions are incorrectly fetched.

Acronyms

• List of acronyms along with their meaning.

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