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Questions and Answers
What are the three main sections of a typical computer system?
What are the three main sections of a typical computer system?
What is the function of the control bus in a computer system?
What is the function of the control bus in a computer system?
The control bus is used to send control signals from the microprocessor to the memory and input/output units.
The data bus in a computer system is bi-directional in nature.
The data bus in a computer system is bi-directional in nature.
True
The control section of a computer system is often referred to as the _____ of the machine.
The control section of a computer system is often referred to as the _____ of the machine.
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Match the following types of registers with their functions:
Match the following types of registers with their functions:
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Which type of parallel computer has all processing units executing the same instruction at any given clock cycle?
Which type of parallel computer has all processing units executing the same instruction at any given clock cycle?
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What is one example of a Processor Arrays SIMD variety?
What is one example of a Processor Arrays SIMD variety?
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Shared memory machines allow all processors to access all memory as global address space.
Shared memory machines allow all processors to access all memory as global address space.
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In Non-Uniform Memory Access (NUMA) systems, memory access across link is ________.
In Non-Uniform Memory Access (NUMA) systems, memory access across link is ________.
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Match the memory architecture with its description:
Match the memory architecture with its description:
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What is the concept termed as when an instruction contains the address of the operand?
What is the concept termed as when an instruction contains the address of the operand?
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Which addressing mode exists when an instruction contains a register address as opposed to a memory address?
Which addressing mode exists when an instruction contains a register address as opposed to a memory address?
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In Register Addressing, the operand values are held in microprocessor registers.
In Register Addressing, the operand values are held in microprocessor registers.
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The modifier M in the address modification principle is also called the ______ or displacement.
The modifier M in the address modification principle is also called the ______ or displacement.
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Match the following addressing modes with their descriptions:
Match the following addressing modes with their descriptions:
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What is the basic idea behind pipelining in computers?
What is the basic idea behind pipelining in computers?
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What does the carry flag indicate in computer systems?
What does the carry flag indicate in computer systems?
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What does the zero flag indicate in computer systems?
What does the zero flag indicate in computer systems?
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What does the overflow flag indicate in computer systems?
What does the overflow flag indicate in computer systems?
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Which of the following flags indicates the most significant bit of the result was negative?
Which of the following flags indicates the most significant bit of the result was negative?
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The stack pointer register contains the address of the top of a ___.
The stack pointer register contains the address of the top of a ___.
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Which unit performs both arithmetic and logical operations in a computer system?
Which unit performs both arithmetic and logical operations in a computer system?
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Read Only Memory (ROM) is volatile, meaning it loses information without power supply.
Read Only Memory (ROM) is volatile, meaning it loses information without power supply.
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Match the memory type with its characteristic:
Match the memory type with its characteristic:
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What is the purpose of addressing modes in microprocessors?
What is the purpose of addressing modes in microprocessors?
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Study Notes
Computer Architecture
- Computer architecture is the science of integrating components to achieve functionality and performance, and it's the logical organization or design of the hardware that makes up the computer system.
General Computer Architecture
- A typical computer system can be divided into three sections:
- Control section: executes instructions and processes data
- Memory section: stores data, instructions, and data
- Input and Output section: handles communications between the computer and the outside world
Buses
- Buses are tiny wires that connect the sections and are divided into three:
- Control bus: sends control signals to memory and I/O units
- Data bus: transfers machine instructions and data between memory and microprocessor
- Address bus: transfers the address of the location in memory or I/O part involved in data transfer
- Buses may be physically the same, carrying data in different directions or addresses at times, and may be shared or multiplexed.
Input/Output Section
- Handles the transfer of data between the computer and external devices or peripherals
- Involves status and control signals as well as data transfer
- I/O section must reconcile time differences between the computer and peripherals, format data properly, handle status and control signals, and supply the required voltage level
- Interrupt control signals receive immediate attention of the control section, causing suspension of its normal activity
Control Section
- Responsible for coordinating the activity of the machine and is the "brain" of the computer
- Functions include:
- Processing data
- Fetching instructions from memory, decoding, and executing them
- Generating timing or control signals
- Transferring data to and from memory and I/O sections
- Performing arithmetic and logical functions
- Recognizing external signals
Memory Section
- Consists of storage units made up of magnetic cores or semiconductor cells
- Storage units are binary constituents with two stable states (0 and 1)
- Memory is organized sequentially into bytes and words, each with a unique address
- Contents are accessed by virtue of their unique addresses
- Memory can be accessed randomly or sequentially
- Access time is the time it takes to find the correct memory location and obtain its content
Registers
- Small memories within the control section
- Consist of binary cells and have a capacity in bytes
- Advantageous because they can be accessed without memory access
- Types of registers include:
- Program Counter (PC)
- Instruction Register (IR)
- Memory Address Register (MAR)
- Accumulators
- General Purpose Registers
- Condition Code or Status Registers
- Stack Pointer (SP)
- Program Counter (PC): contains the address of the next instruction
- Instruction Register (IR): holds instructions until they are decoded
- Memory Address Register (MAR): holds the address of data in memory
- Accumulators: temporary storage used during calculations
- General Purpose Registers: perform a variety of functions
- Condition Code or Status Registers: indicators of the state or present condition inside the computer system
- Stack Pointer (SP): contains the address of the top of a stack
Arithmetic Units
- Perform arithmetic and logical operations
- Examples include:
- Binary adder
- Binary subtractor
- Multiplication and division units
- Logical AND, OR, and NOT units
- Shift and rotation units
Instruction Handling Areas
- CPU must translate instructions into control signals
- CPU performs an instruction cycle, which includes:
- Fetching the instruction from memory
- Decoding and executing the instruction
- Fetching the next instruction
Types of Memory
- ROM (Read Only Memory): permanent storage that can only be read
- RAM (Random Access Memory): read/write memory that is volatile and can be updated or corrected
- PROM (Programmable Read Only Memory): contents are determined by users or manufacturers
- EPROM (Erasable PROM): contents can be erased through exposure to high-intensity short-wave ultraviolet light
- EAROM (Electrically Alterable ROM): contents can be changed electrically without removal from the circuit board### Registers and Instruction Formats
- Registers may have varied lengths, and special instructions may be available to load and manipulate their contents.
- Most microprocessors have an arithmetic unit with a simple bus structure, where one operand is an accumulator and the other operand is a temporary register.
- Instruction formats have two components:
- Op-Code field: specifies how data is to be manipulated.
- Address field: indicates the address of a data item.
Instruction Formats
- 3-Address Format:
(OP-Code) Addr 1, Addr 2, Addr 3- Example:
MUL A, B, C; C = A * B
- Example:
- 2-Address Format:
(OP-Code) Addr1, Addr2- Example:
MOV A, R1; R1 = A
- Example:
- 1-Address Format:
(OP-Code) Addr- Example:
LDA B; Acc = B
- Example:
- 0-Address Format:
(OP-Code)- Example:
NOP,DEC,INC
- Example:
Address Modes
- Inherent or Implied Addressing: Op-code implies the address of the operand.
- Example:
CMA; Complement Accumulator register
- Example:
- Immediate Addressing: Instruction contains the operand value.
- Example:
ADD #16, R0; R0 = R0 + 16
- Example:
- Absolute or Direct Addressing: Instruction contains the address of the operand.
- Example:
MOVE 2000, R0; R0 = M(2000)
- Example:
- Indirect Addressing: Instruction contains the address of an address of the operand.
- Example:
MOVE (2000), R0; R0 = M(M(2000))
- Example:
- Register Addressing: Instruction contains a register address as opposed to a memory address.
- Example:
ADD R1, R0; R0 = R1 + R0
- Example:
- Index Mode: Value of RA is included in the instruction, and the register contains the value M.
- Example:
LDA 0100 (X)
- Example:
- Base Register Mode: Parameter RA is held in a separate register, and the modifier is included in the instruction.
- Example: Used in segmented memory systems where the base register holds the base address of a segment.
- Relative Addressing Mode: Program counter is configured as the base register.
- Example:
JP 0248H
- Example:
Pipelined Computers
- Pipelining is a technique to improve CPU speed by adding parallel elements to the computer's arithmetic and control elements.
- It allows for multiple instructions to be worked on in parallel, increasing the throughput of the computer.
- The pipeline consists of five stages:
- Fetch the instruction
- Decode the instruction
- Generate operand address
- Fetch operands
- Execute the instruction
- Pipelining can be affected by branch instructions and operand modifications.
Interrupts
- An interrupt is a temporary transfer of control from a currently running program to an interrupt service routine.
- Interrupts can be externally generated (by I/O devices) or internally generated (by the CPU itself).
- The CPU must save its state before executing the interrupt service routine and restore it afterwards.
Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC)
- CISC architectures have a large number of instructions, which can lead to complications and heat generation.
- RISC architectures have a small set of simple instructions, which can be executed rapidly.
- RISC architectures have additional features, such as:
- A small chip area
- A simple instruction set
- Few addressing modes
- A memory hierarchy with cache memory
- A pipelined processor
- Control is in gates and flip-flops
Parallel Computing
- Von Neumann Architecture: A stored-program concept, where the CPU executes a stored program that specifies a sequence of read and write operations on the memory.
- Flynn's Classical Taxonomy: Classifies parallel computers according to the number of instructions and data streams.
- SISD: Single Instruction, Single Data
- SIMD: Single Instruction, Multiple Data
- MISD: Multiple Instruction, Single Data
- MIMD: Multiple Instruction, Multiple Data
Parallel Computer Memory Architectures
-
Shared Memory: All processors can access all memory as a global address space.
-
Uniform Memory Access (UMA): Identical processors and equal access times to memory.
-
Non-Uniform Memory Access (NUMA): Processors do not have equal access times to all memories.### Synchronization in Distributed Memory Systems
-
Programmers are responsible for ensuring correct access to global memory using synchronization constructs.
-
Distributed memory systems require a communication network to connect inter-processor memory.
-
Each processor has its own local memory, and memory addresses in one processor do not map to another processor.
-
There is no concept of global address space across all processors, and changes made to local memory do not affect other processors.
-
The concept of cache coherency does not apply, and programmers must explicitly define data communication and synchronization between tasks.
Characteristics of Distributed Memory Systems
- Memory is scalable with the number of processors, increasing proportionately with the number of processors.
- Each processor can rapidly access its own memory without interference and without the overhead of cache coherency.
- Cost-effective, using commodity, off-the-shelf processors and networking.
Disadvantages of Distributed Memory Systems
- Programmers are responsible for many details associated with data communication between processors.
- It may be difficult to map existing data structures based on global memory to this memory organization.
- Non-uniform memory access (NUMA) times.
Hybrid Distributed-Shared Memory Architecture
- Combines the advantages of shared and distributed memory architectures.
- The shared memory component is usually a cache-coherent SMP machine.
- The distributed memory component is the networking of multiple SMPs.
- SMPs only know about their own memory, and network communications are required to move data from one SMP to another.
Comparison of Shared and Distributed Memory Architectures
- Shared memory architectures (CC-UMA, CC-NUMA) have limitations in scalability, while distributed memory architectures can scale to 1000s of processors.
- Distributed memory architectures require explicit communication and synchronization between processors, increasing programmer responsibility.
- Hybrid architectures combine the advantages of both, but have their own set of challenges, such as system administration and programming complexity.
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Description
Learn about the fundamental concepts of computer architecture, including system features, design variations, and integration of components for optimal functionality and performance.
