Computer Architecture and Parallelism

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Questions and Answers

What is the main idea behind Tomasulo's algorithm?

To improve the performance of VLIW architectures
To implement out-of-order execution processors (correct)
To enable in-order execution of instructions
To reduce the number of instructions in a program

What is a characteristic of VLIW architectures?

They are used in high-performance computing applications
They rely on the compiler to schedule instructions (correct)
They are designed for real-time systems
They use complex hardware to schedule instructions

What is a challenge in RISC processors?

There are too few instructions in the instruction set
Instructions have very different execution times (correct)
Instructions have similar execution times
There are too many instructions in the instruction set

What is a consequence of out-of-order completion?

WAR and WAW dependencies may occur (C) Signup and view all the answers

What is the goal of advancing in ILP exploration?

To allow more than one instruction to be issued at a time (D) Signup and view all the answers

What is an example of a VLIW processor?

Itanium2 (D) Signup and view all the answers

What is a problem with allowing more than one instruction to be issued at a time?

It can lead to WAR and WAW dependencies (C) Signup and view all the answers

What is the main challenge in dynamic scheduling?

Dealing with WAR and WAW dependencies (D) Signup and view all the answers

What type of dependencies exist between instructions 1 and 2 in the original code?

WAR dependencies (B) Signup and view all the answers

Why would changing the execution order of instructions 1, 3, 2, 4 decrease delays?

To increase instruction-level parallelism (B) Signup and view all the answers

What technique is used to avoid false WAR and WAW dependencies?

Register renaming (D) Signup and view all the answers

What is the basic premise of out-of-order execution?

Allow for out-of-order execution, as long as the very same result of in-order execution is preserved (D) Signup and view all the answers

What type of dependencies exist between instructions 2 and 3 in the original code?

WAW dependencies (D) Signup and view all the answers

What is the main goal of dynamic scheduling?

To reduce dependencies between instructions (C) Signup and view all the answers

What is the result of allowing out-of-order execution with register renaming?

Increased instruction-level parallelism (A) Signup and view all the answers

What is the main advantage of out-of-order completion?

Increased instruction-level parallelism (D) Signup and view all the answers

What is the main goal of Instruction-Level Parallelism (ILP)?

To execute multiple instructions simultaneously (C) Signup and view all the answers

What is the limitation imposed by pipelining?

Clock cycles per instruction (CPI) equal to 1 (D) Signup and view all the answers

What is the main issue with compiler-based approaches to ILP exploration?

They are successful only in domain-specific environments (B) Signup and view all the answers

What is the advantage of pipelining?

Reduced idle time and inefficiency (D) Signup and view all the answers

What is the purpose of out-of-order execution?

To execute instructions out of the order they are received to improve performance (C) Signup and view all the answers

What is the issue with dynamic scheduling?

It is not effective in resolving WAW dependencies (C) Signup and view all the answers

What is the limitation of ILP exploration?

It is limited by the availability of parallelism (C) Signup and view all the answers

What is the Intel Itanium series known for?

Its aggressive compiler-based approach to ILP exploration (C) Signup and view all the answers

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Study Notes

Instruction-Level Parallelism (ILP)

ILP is a software-based approach to find parallelism statically at compile time.
Aggressive compiler-based proposals have been tried since the 1980s, but have been successful only in domain-specific environments.

Pipelining

Pipelining creates a theoretical barrier, with clock cycles per instruction (CPI) equal to 1.
Without pipelining, there is idle time and inefficiency.
With pipelining, CPI is limited to 1.

Tomasulo's Algorithm

Tomasulo's algorithm enables out-of-order execution processors to be implemented.

VLIW (Very Long Instruction Word)

VLIW is a type of ILP that orders instructions in packages by the software (compiler).
It is used in embedded systems, which have less complex hardware.
VLIW is also known as Explicitly Parallel Instruction Computing (EPIC).
An example of VLIW is the Itanium2 processor.

Advancing in ILP

Even in RISC processors, there are instructions with very different execution times.
The problem with this is that it limits the CPI.
The solution is to allow more than one instruction to be issued at the same time.

Out-of-Order Execution

Out-of-order execution allows instructions to be issued in a different order than they were received.
This can lead to potential out-of-order completion.

WAR and WAW Dependencies

WAR (Write After Read) and WAW (Write After Write) dependencies are problems that arise in out-of-order execution.
These dependencies can lead to incorrect results.

Dynamic Scheduling Problems

Dynamic scheduling problems occur when instructions are executed out of order.
These problems can lead to dependencies and incorrect results.

False Dependencies Solution

The solution to false dependencies is to allow for out-of-order execution while preserving the same result as in-order execution.
This is achieved through registers renaming, which avoids false WAR and WAW dependencies.