Combinational Logic Gates in CMOS 2

What is the primary difference between static and dynamic CMOS circuits?

The ability to temporarily store signal values

How many transistors are required for a fan-in of N in a static CMOS circuit?

2N

What happens to the output node during the precharge phase of a dynamic CMOS circuit?

It is precharged to VDD

What is the purpose of the evaluation FET in a dynamic CMOS circuit?

To eliminate static power consumption Signup and view all the answers

What determines the mode of operation in a dynamic CMOS circuit?

The clock signal (CLK) Signup and view all the answers

What happens to the output if the pull-down network is turned off during the evaluation phase?

It remains unchanged Signup and view all the answers

What is a disadvantage of precharging internal nodes using a clock-driven transistor?

Increased power consumption Signup and view all the answers

What is a challenge in dynamic design?

High impedance of output node Signup and view all the answers

What is the effect of capacitive coupling in a dynamic NAND gate?

Output node is highly sensitive to crosstalk Signup and view all the answers

What happens when a wire is routed over a dynamic node?

Capacitive coupling occurs, potentially distorting the state of the floating node Signup and view all the answers

What is backgate coupling?

A type of capacitive coupling Signup and view all the answers

What is the result of backgate coupling in a dynamic NAND gate?

The output of the static NAND gate drops, but not all the way to 0V, causing static power dissipation Signup and view all the answers

What is the primary cause of clock-feedthrough in dynamic circuits?

Capacitive coupling between clock input and dynamic output node Signup and view all the answers

What is the purpose of setting all inputs to 0 during precharge in cascaded n-type dynamic gates?

To ensure correct operation by preventing inadvertent discharge Signup and view all the answers

What happens when clock-feedthrough occurs in a dynamic circuit?

The output of the dynamic node rises above VDD Signup and view all the answers

What consists of Cgd of the precharge device in dynamic circuits?

Both overlap and channel capacitances Signup and view all the answers

What is the consequence of clock-feedthrough in dynamic circuits?

Forward-biased junction diodes of precharge transistor Signup and view all the answers

What ensures correct operation in cascaded n-type dynamic gates?

Guaranteeing a single 0→1 transition during evaluation Signup and view all the answers

What happens to Out1 during precharge when CLK is 0?

It is charged to VDD Signup and view all the answers

What is the condition for Out1 of the n-tree gate to make a 1→0 transition?

CLK must be 1 Signup and view all the answers

Why are p-tree blocks slower than n-tree modules?

Due to lower current drive of PMOS transistors Signup and view all the answers

What is the requirement for cascading dynamic gates?

n-tree blocks can follow p-tree gates without any problems Signup and view all the answers

What is the disadvantage of np-CMOS?

Slower p-tree blocks due to lower current drive of PMOS transistors Signup and view all the answers

What is the effect of charge sharing on the output voltage in dynamic circuits?

It results in a drop in the output voltage that cannot be recovered Signup and view all the answers

What determines which case of charge sharing is valid?

The capacitance ratio Signup and view all the answers

What is the most effective way to deal with charge redistribution?

By precharging the internal node Signup and view all the answers

What is the desirable condition for the value of VTp?

It should be kept below |VTp| Signup and view all the answers

What are the two scenarios to consider in charge sharing, assuming the initial conditions at time zero?

VX = VDD – VTn(VX) and VX reaches the same value as Vout Signup and view all the answers