Combinational Logic Gates in CMOS 1
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Questions and Answers

What is the primary advantage of CMOS structures?

  • Low performance with high static power dissipation
  • High speed with high power consumption
  • High power consumption with high static power dissipation
  • Robustness, good performance, and low power consumption with no static power dissipation (correct)

What is the difference between combinational and sequential logic gates?

  • Combinational gates are non-regenerative, while sequential gates are regenerative
  • Combinational gates are regenerative, while sequential gates are non-regenerative
  • Combinational gates have no intentional connections between outputs and inputs, while sequential gates do (correct)
  • Combinational gates have intentional connections between outputs and inputs, while sequential gates do not

What is the relationship between the output and input signals in a combinational logic gate?

  • The output is a function of the output signals
  • The output is a function of previous input signals
  • The output is a function of the power supply voltage
  • The output is a function of the current input signals (correct)

What is the characteristic of a static CMOS circuit?

<p>The output of the gate is connected to VDD or Vss via a low-resistance path (B)</p> Signup and view all the answers

What is the difference between dynamic and static CMOS circuits?

<p>Dynamic circuits rely on temporary storage of signal values, while static circuits do not (C)</p> Signup and view all the answers

What is the relationship between the output and previous input signals in a sequential logic gate?

<p>The output is a function of previous input signals (A)</p> Signup and view all the answers

What is the state of an NMOS transistor when the controlling signal is high?

<p>On (A)</p> Signup and view all the answers

What is the state of a PMOS transistor when the controlling signal is high?

<p>Off (B)</p> Signup and view all the answers

What is the relationship between the pull-up and pull-down networks in a complementary CMOS structure?

<p>They are dual networks (B)</p> Signup and view all the answers

How is the other network (PUN or PDN) obtained in a CMOS gate construction?

<p>Using the duality principle (C)</p> Signup and view all the answers

What is the purpose of the duality principle in CMOS gate construction?

<p>To obtain the other network (PUN or PDN) (D)</p> Signup and view all the answers

What is the result of combining the PDN and PUN in a CMOS gate construction?

<p>A complete CMOS gate (B)</p> Signup and view all the answers

What is the main factor that affects the propagation delay of complementary CMOS gates?

<p>Input patterns (C)</p> Signup and view all the answers

What happens when devices are added in series in a CMOS circuit?

<p>The circuit becomes slower (C)</p> Signup and view all the answers

What is the probability that the output node of a 2-input static NOR gate equals one?

<p>p_a + p_b - (p_a * p_b) (B)</p> Signup and view all the answers

What occurs in a multistage logic network due to the finite propagation delay between logic blocks?

<p>Spurious transitions called glitches occur (C)</p> Signup and view all the answers

What is the worst-case pull-down transition in a 2-input NOR gate?

<p>One input is high and the other is low (A)</p> Signup and view all the answers

Why must devices be made wider in a CMOS circuit?

<p>To avoid a performance penalty (C)</p> Signup and view all the answers

What happens to the higher order even outputs in a chain of NAND gates during a transition from 0 to 1?

<p>They start to discharge and the voltage drops (B)</p> Signup and view all the answers

What is the reason for the initial output of a chain of NAND gates being 1 when all inputs go simultaneously from 0 to 1?

<p>One of the inputs was 0 (A)</p> Signup and view all the answers

What is the condition for the output to be high in a 2-input NOR gate?

<p>Both inputs are low (D)</p> Signup and view all the answers

What is the term for the probability that the output node of a static logic gate transitions from 0 to 1?

<p>Output transition probability (C)</p> Signup and view all the answers

How can the NMOS devices in a 2-input NOR gate be sized to match the delay of an inverter?

<p>By keeping them the same width as the NMOS device in the inverter (A)</p> Signup and view all the answers

What happens to the output node of a chain of NAND gates after the correct input ripples through the network?

<p>The output node goes high (C)</p> Signup and view all the answers

What is the minimum voltage that PDN1 must be able to bring Out to for M2 to turn on?

<p>VDD-|VTp| (A)</p> Signup and view all the answers

What is the delay from the input to Out in the transient response of the AND/NAND gate?

<p>197 psec (C)</p> Signup and view all the answers

What is the purpose of the switch driven by B in the pass-transistor logic AND gate?

<p>To ensure a low-impedance path to the supply rails (B)</p> Signup and view all the answers

How do pass-transistor logic gates aim to reduce the number of transistors required?

<p>By allowing primary inputs to drive gate terminals as well as source/drain terminals (A)</p> Signup and view all the answers

What is the function of M1 in the DCVSL gate?

<p>To discharge Out to GND (A)</p> Signup and view all the answers

What is the size of the cross-coupled PMOS devices in the DCVSL gate?

<p>1.5um/0.25um (D)</p> Signup and view all the answers

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