Combinational Logic Gates in CMOS 1

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What is the primary advantage of CMOS structures?

Low performance with high static power dissipation

High speed with high power consumption

High power consumption with high static power dissipation

Robustness, good performance, and low power consumption with no static power dissipation (correct)

What is the difference between combinational and sequential logic gates?

Combinational gates are non-regenerative, while sequential gates are regenerative

Combinational gates are regenerative, while sequential gates are non-regenerative

Combinational gates have no intentional connections between outputs and inputs, while sequential gates do (correct)

Combinational gates have intentional connections between outputs and inputs, while sequential gates do not

What is the relationship between the output and input signals in a combinational logic gate?

The output is a function of the output signals

The output is a function of previous input signals

The output is a function of the power supply voltage

The output is a function of the current input signals (correct)

What is the characteristic of a static CMOS circuit?

The output of the gate is connected to VDD or Vss via a low-resistance path Signup and view all the answers

What is the difference between dynamic and static CMOS circuits?

Dynamic circuits rely on temporary storage of signal values, while static circuits do not Signup and view all the answers

What is the relationship between the output and previous input signals in a sequential logic gate?

The output is a function of previous input signals Signup and view all the answers

What is the state of an NMOS transistor when the controlling signal is high?

On Signup and view all the answers

What is the state of a PMOS transistor when the controlling signal is high?

Off Signup and view all the answers

What is the relationship between the pull-up and pull-down networks in a complementary CMOS structure?

They are dual networks Signup and view all the answers

How is the other network (PUN or PDN) obtained in a CMOS gate construction?

Using the duality principle Signup and view all the answers

What is the purpose of the duality principle in CMOS gate construction?

To obtain the other network (PUN or PDN) Signup and view all the answers

What is the result of combining the PDN and PUN in a CMOS gate construction?

A complete CMOS gate Signup and view all the answers

What is the main factor that affects the propagation delay of complementary CMOS gates?

Input patterns Signup and view all the answers

What happens when devices are added in series in a CMOS circuit?

The circuit becomes slower Signup and view all the answers

What is the probability that the output node of a 2-input static NOR gate equals one?

p_a + p_b - (p_a * p_b) Signup and view all the answers

What occurs in a multistage logic network due to the finite propagation delay between logic blocks?

Spurious transitions called glitches occur Signup and view all the answers

What is the worst-case pull-down transition in a 2-input NOR gate?

One input is high and the other is low Signup and view all the answers

Why must devices be made wider in a CMOS circuit?

To avoid a performance penalty Signup and view all the answers

What happens to the higher order even outputs in a chain of NAND gates during a transition from 0 to 1?

They start to discharge and the voltage drops Signup and view all the answers

What is the reason for the initial output of a chain of NAND gates being 1 when all inputs go simultaneously from 0 to 1?

One of the inputs was 0 Signup and view all the answers

What is the condition for the output to be high in a 2-input NOR gate?

Both inputs are low Signup and view all the answers

What is the term for the probability that the output node of a static logic gate transitions from 0 to 1?

Output transition probability Signup and view all the answers

How can the NMOS devices in a 2-input NOR gate be sized to match the delay of an inverter?

By keeping them the same width as the NMOS device in the inverter Signup and view all the answers

What happens to the output node of a chain of NAND gates after the correct input ripples through the network?

The output node goes high Signup and view all the answers

What is the minimum voltage that PDN1 must be able to bring Out to for M2 to turn on?

VDD-|VTp| Signup and view all the answers

What is the delay from the input to Out in the transient response of the AND/NAND gate?

197 psec Signup and view all the answers

What is the purpose of the switch driven by B in the pass-transistor logic AND gate?

To ensure a low-impedance path to the supply rails Signup and view all the answers

How do pass-transistor logic gates aim to reduce the number of transistors required?

By allowing primary inputs to drive gate terminals as well as source/drain terminals Signup and view all the answers

What is the function of M1 in the DCVSL gate?

To discharge Out to GND Signup and view all the answers

What is the size of the cross-coupled PMOS devices in the DCVSL gate?

1.5um/0.25um Signup and view all the answers