Bus Interfaces and Classifications

Bus Interfaces and Classifications

• Nodes of a bus are typically electronic boards

• Nodes can be modeled as master (M) or slave (S) user modules

• Examples of user modules include MPU (Microprocessor Unit), memory devices, and I/O controllers

• A bus interface facilitates communication between the user module (master or slave) and the bus

• A clocked interface has its state machine paced by a clock

• A clocked protocol has both entities paced by the same clock signal

• Functional modules manage bus access elements like requests, arbitration, grants, preemption, and DMA transfers

• Bus timing signals are also managed by Functional modules

Associated Signals

• Signals differ from power supply lines (V+, V-, Gnd) by carrying information as a physical parameter (electricity)
• Logical signals can be level-sensitive (active in high or low state) or edge-sensitive (active on one or both edges)
• Signals were originally amplifications of those from the microprocessor
• Bus signals are now independent of the microprocessor due to generic electronics separate from the electrical interface
• Bus signals are separated into families based on their function:
• Address transfer bus: Carries the address from master to slaves
• Data transfer bus: Uses n signals from the microprocessor D[n-1:0] and can transfer binary words in a smaller format
• Control bus: Access control signals (memory and I/O read/write) and address type signals (memory/I/O)
• Status bus: Reports bus errors, involving other masters and the memory system
• Access arbitration bus: Manages access to transfer buses using request, grant, and state signals; it can involve interruption and DMA transfer requests
• Synchronization bus: Carries clock signals like constant clock and bus clock
• Utility bus: Generates start and stop sequences; a specialized slow serial bus can coexist

Interfacing Logic

• The main purpose of interfacing logic is to isolate and amplify all signals
• It shifts voltage levels between technology and logical families
• Interfacing logic consists of coupled drivers (line amplifiers) and receivers

Transmission Lines

• A transmission line is a communication path in a bus. For example, electrical wire, ribbon cable, or PCB trace, with return current through ground
• Four electrical parameters characterize transmission lines:
• R: Resistance per unit length (Ω/m)
• L: Inductance per unit length (H/m)
• C: Capacitance per unit length (C/m)
• G: Conductance per unit length (S/m)

Signal Integrity

• Noise interferes with the useful signal, causing transmission errors -Crosstalk: Interference from one line (aggressor) on another (victim) -Noise sources: RFI (Radio-Frequency Interference) and EMI (Electromagnetic Interference), within EMC (Electromagnetic Compatibility) and current loops -Shielding protects against electromagnetic interference -When propagation times match the signal period, managing clock signals becomes vital

Multibus Architecture

• Initially, all entities shared a single shared/linear bus inside a computer (CPU, memory, devices, display terminal)
• Segmented Buses:
• Each segment is a bus portion
• Logical bus splitting allows communication between masters and slaves
• Classical line terminations are included
• Hierarchical Buses:
• Cluster of elements communicate via a locally segmented bus that are linked by a global bus
• The inter-cluster bus forms a bus hierarchy
• Multiple Buses:
• Parallel architecture for calculators in the 1980s used multiple processors, storage systems, and buses
• Allows for concurrent communication
• The concept of hierarchy can also be applied here
• Bridge:
• Links two buses together and must respect their electrical and temporal specifications
• It isolates and amplifies the signals (buffering) via a driver (signal amplifier)

Classification of Digital System Buses

• Local Bus:
• Found at the component level on the PCB
• Microprocessor bus is the sole initiator of exchanges unless a DMA controller is present
• Memory Buses:
• A controller serves ranks of memory devices via multiple channels or memory bus
• Interleaving access is established by increasing the number of channels
• Link Buses:
• Links microprocessors to each other or to a bridge via packets
• Communication lacks cycles
• Expansion Slot Bus:
• Connectors allow insertion of I/O interface cards (expansion cards)
• Expansion Buses:
• Microprocessor board enables small I/O expansion board at the board-level
• Supports interrupt and transfer requests like DMA
• I/O Buses:
• Links one or more devices to I/O controllers
• Can depend on a group of devices (ATA, SATA, SCSI)
• Backplane and Centerplane Buses:
• A backplane bus enables communication between connected electronic cards (backplane interface)
• Printed circuit board (motherboard) version of the ribbon cable
• Parallel copper traces/serial traces link the slot connectors for daughterboard slots;
• "Centerplane" bus minimizes connector distances by placing connectors throughout the printed circuit board
• Fieldbus:
• Associated with the "Programmable Logic Controller" (PLC) and interacts via measurement instruments, sensors, and actuators
• More resilient in noisy industrial environments, in contrast to "computer bus"
• SoC: from Bus to Network:
• System on a Chip integrates components from the system level (microprocessors, memories, I/O controllers) down to a single chip
• Power Bus:
• Supplies power to a computer system which requires different precise voltages (e.g., +3.3 V, +5 V, +12 V ±5%)
• Values are tied to logic technology or components like HDD motors