Week 04-Silicon Crystal Growth PDF

1 Crystal growth Courtesy: Prof. Chad Young Semiconductor Processing Technology Prof. Walter Hu ...

1 Crystal growth Courtesy: Prof. Chad Young Semiconductor Processing Technology Prof. Walter Hu  2 Sand to silicon wafer Sand (SiO2) Metallurgical grade SiHCl3 Quartzite Si (MGS) ($ 2 /kg) ($ 20 /kg) 95~98% pure Arc Fluidized bed furnace reaction Vapor w/HCl and deposition distillation Electronic grade Polished Si wafer Pure Si crystal Si (EGS) (poly-Si) ($ 1300 /kg) ($ 400 /kg) (> $ 80 /kg) Wafering & Crystal polishing growth (CZ, FZ) Source: http://www.fullman.com/semiconductors/semiconductors.html Semiconductor Processing Technology  3 Sand to EGS  Start from quartzite (sandstone)  Abundant, relatively pure form of SiO2 in nature Wikipedia  Refining powered quartzite with coke to MGS  2C+SiO2→Si(liquid)+ 2CO(gas) - arc furnace (~2,000°C)  Majority of usage of Si is MGS (silicone,...)  MGS to EGS  Si(S)+ HCl(g)→SiHCl3(l) (fractional distillation)  SiHCl3 is liquid at RT  SiHCl3(g)+2H2(g)→Si(s)+6HCl (CVD)  Si deposited on a thin Si rod, EGS poly-Si formed, impurities < ppb  EGS to Si wafer  Crystal growth  CZ (Czochralski)  FZ (Float zone) Semiconductor Processing Technology  4 Ingot to wafer Slicing CZ FZ Ingot Si wafers for IC manufacturing Polishing Lapping Sources: http://www.fullman.com/semiconductors/semiconductors.html http://www.msil.ab.psiweb.com/english/msilhist0-e.html Semiconductor Processing Technology  5 Crystal Growth: FZ FZ (Float zone) https://www.youtube.com/watch?v=pgX4Xlw0NbM Polysilicon Ingot RF Coil Single Crystal Si sc-Si wafer seed layer Semiconductor Processing Technology  6 Crystal Growth: CZ CZ (Czochralski) https://www.youtube.com/watch?v=2qLI-NYdLy8 Seed Single Crystal Silicon Quartz Crucible Water Cooled Chamber Heat Shield Carbon Heater Graphite Crucible Crucible Support Spill Tray Electrode Semiconductor Processing Technology  7 Doped wafers - segregation Solubility https://www.pv-magazine.com/2018/04/14/the-weekend-read-chinas-monocrystalline-boom/ https://www.youtube.com/watch?v=JSTDq5dZx9w Lower CS ↑ ↑ ↑ Pull Higher CS Semiconductor Processing Technology  8 Normal CZ growth model Seed  Molten Si freezes between isotherm x1 & x2 dx C  Heat conduction is dominant  Heat conduction (dominant in the solids) B Solid Si Isotherm X2  Heat transfer by collisions between A atoms/molecules  Described by Fourier’s law Liquid Si Isotherm X1  Heat flux vector (q”=q/A) is proportional to and in the opposite direction of the temperature gradient. CL CS solid liquid Normal CZ growth model Semiconductor Processing Technology Heat flow  9 Normal CZ growth model (cont'd) Seed  Heat balance in the freezing zone  Heat flow in from melt + latent heat C = heat flow away from the freezing zone to dx the solid B Isotherm X2 Solid Si A Liquid Si Isotherm X1 L  latent heat of fusion dm  amount of freezing per unit time dt k L  thermal conductivity of liquid dT  thermal gradient at isotherm x1 dx 1 k S  thermal conductivity of solid dT  thermal gradient at x 2 dx 2 https://www.youtube.com/watch?v=F1x 9g90WIes Semiconductor Processing Technology  10 Normal CZ growth model (cont'd)  Simplification  Neglecting the 2nd term gives "min. heat" must be taken away from the freezing interface  Assume A1 = A2 = A  The rate of crystal growth vP : pull rate N : density of Si , vP, max : maximum pull rate  Heat conducted to the solid (away from freezing zone) are lost by radiation C (Stefan-Boltzmann law) Seed   : emissivity of Si (~0.55, 0    1)   : Stefan-Boltzmann constant (5.67 x 10-5 dx C [erg/cm2-sec-K4]) B Isotherm X2 Solid Si A Liquid Si Isotherm X1 Semiconductor Processing Technology  11 Normal CZ growth model (cont'd) Seed  Heat conduction up the crystal (B) C dx Differentiating B Isotherm X2 Solid Si A Liquid Si Isotherm X1 𝑑𝑄 = 2𝜋𝑟𝑑𝑥 𝜎𝜀𝑇 𝑑𝑄 = 2𝜋𝑟 𝜎𝜀𝑇 𝑑𝑥  ks, Si ~ 1/T , when T < 1000°C, we can use 𝑘 =𝑘 𝑇 kM : conductivity at m.p. 𝑇  Solving diff. eqn. & evaluating at x = 0, we get , Semiconductor Processing Technology  12 Doped wafers using normal CZ model 10 VS, CS Boron 1 CS/CO VO, IO, CO IL, CL Phosphorus, Arsenic V0 : initial volume in the melt I0 : initial number of impurities in the melt 0.1 C0 : initial imp. conc. in the melt Antimony VL : volume in the melt IL : number of impurities in the melt CL : imp. conc. in the melt 0.01 0 0.2 0.4 0.6 0.8 1 VS : impurity volume in the solid Fraction of Melt Solidified CS : imp. conc. in the solid Boron (k0=0.8) relatively flat function of time if k0 ≠ 1 P, As : heavier doping as crystal grows Semiconductor Processing Technology  13 Modified CZ growth model  Normal CZ growth model can CL be modified CS  Rejected impurities (k0 < 1) solid liquid cannot be removed right away Normal CZ growth model from solid/liquid interface CL' CL CS solid liquid Modified CZ growth model Make keff ~1  achieving more uniformly doped wafer Semiconductor Processing Technology  14  The only equation we may be working with: C S  k 0 C 0 1  X  k 0 1 where X is the portion of the melt already turned into solid (X=0 at the beginning, X=1 at the end) Cs is doping concentration in the resulting solid Co is doping concentration in the initial melt k0 is segregation coefficient (ratio of solubility of the dopants in the solid over solubility in the melt) At the beginning (X=0), Cs = k0C0 At 90% (X=0.9), Cs = k0C0 0.1k0-1 = 10(1-k0) k0C0 ~ 10 k0C0 for very small k0 Semiconductor Processing Technology  15 Unintentional impurities in Si crystal Oxygen : primarily interstitial Carbon: primarily substitutional Semiconductor Processing Technology  16 Doped wafers using FZ  In the float zone process, dopants and other impurities tend to stay in the liquid and therefore refining can be accomplished, especially with multiple passes L Zone CS(x) CO  For uniform doping, some FZ done in gaseous dopant (PH3, B2H6) dx environment Semiconductor Processing Technology  17 Wafer size: the larger the better? 18" https://geardiary.com/ Semiconductor Processing Technology  18 Flats on Si ingot Semiconductor Processing Technology  19 Surface crystal orientation - Flats in Si wafers 200mm or larger diameter wafers have a Small diameter wafers have flats notch Semiconductor Processing Technology  20 Semiconductor Processing Technology End of the slide set