MOSFETs.pdf

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) BACKGROUND This falls under three terminal device categories; current through two terminals is controlled by the voltage applied at the third terminal. That is a voltage controlled current source (acts as an amplifi...

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) BACKGROUND This falls under three terminal device categories; current through two terminals is controlled by the voltage applied at the third terminal. That is a voltage controlled current source (acts as an amplifier). Also, the current flow at a terminal can be varied through voltage application between the other two terminals (acts as a switch). Have multitude of applications ranging from signal amplification to digital logic circuits. MOSFETs occupy small area on the silicon IC chip, thus possible to design billions of the same on a single IC chip (VLSI technology) required in memory circuits and microprocessors. Have played significant role in mixed signal IC chips incorporating amplifiers, filters, memory circuits, and digital switches. Path of development:@ Bell Labs, William Shockley in 1952 proposed field effect transistors followed by Dawon Kahng and Martin Atalla in 1960 developing MOSFETs. ESSENTIALS Structural Basics and Operation in Detail An enhancement type n-MOSFET The gate current is extremely small of the order of fA The source and drain regions (symmetrical layout) always remain reversed biased having a channel in between of length L and width W. L normally is in the range of 0.03 to 1 μm. W normally is in the range of 0.05 to 100 μm. The MOSFET operation can be divided into the following segments and the voltage current characteristics can be realized 1. Zero Gate Voltage , i.e. VGS = 0 2. Gate Voltage Application , i.e. VGS is positive and beyond a certain threshold 3. Small Value of Drain to Source Voltage (VDS > 0) 4. Increasing the level of VDS 5. The level of VDS is beyond a certain threshold The necessary developments in the process following the stages given above are shown below: Stage 1 Back to back diodes in the path with no control voltage at the gate terminal; NO conduction channel, hence absence of current flow. Stage 2 Onset of positive gate to source voltage (nMOS under consideration); FORMATION of conduction channel under the gate region in between drain and source. Channel conduction is initiated at VGS = Vt (Threshold Voltage) Conduction is applicable when vGS > Vt OR Overdrive voltage is present, vOV = vGS - Vt Magnitude of the electron charge in the channel |Q| = COX(WL)vOV , where COX is the oxide capacitance per unit gate area with COX = ЄOX / tOX Stage 3 A small value of drain to source voltage will keep the channel unaffected, i.e. vGS is constant throughout the channel from source end to drain end. Hence, Q remains unaltered. The relevant equations describing the drain to source current flow are: Process transconductance parameter (unit A/V2) Aspect ratio (dimensionless) MOSFET transconductance parameter Linear zone of operation in iD – vDS characteristic Stage 4 VDS appears as a voltage drop across the length of the channel. At the source end of the channel the potential = Vt + vOV At the drain end of the channel the potential between Gate and Drain, vGD = Vt + vOV - vDS The structural effect and the representation for the drain current is given below: The drain current iD , hence gets modified following a non-linear pattern of increase with respect vDS , i.e. OR Stage 5 This is the final stage of current determination, i.e. formation of saturation zone owing to channel pinch off at the drain end. At the onset of saturation, vDS = vOV and therefore vGD = Vt Beyond this point further increase in vDS has almost no effect on the channel shape and charge and the drain current remains constant at the value obtained at vDS = vOV The saturation current is OR The saturation voltage VDSat can be represented as Note that any increase in vDS beyond VDSat appears as a voltage drop across the depletion region at the drain end and all the electrons passing through the pinched off region are accelerated to the drain terminal. The structural consequence is given on the next page. The entire characteristic comprising all the stages of operation is depicted below Finally the circuit symbol, enhancement nMOSFET in operation, generalized iD-vDS & iD- vGS characteristics, and large signal equivalent circuit model under saturation are shown below: Circuit Symbols: nMOSFET in operation: Generalized iD-vDS characteristics: Generalized iD-vGS characteristics: Large signal equivalent circuit model under saturation: An enhancement type p-MOSFET Here, the essentials are just the opposite, i.e. vGS < Vt for channel conduction with & Circuit symbols: An enhancement pMOSFET in operation: iD-vSD characteristic: Equivalently, OR NEW concepts, λ and VA , is explored on the next page. Cross section of a c-MOSFET For cMOS configuration comprising nMOS and pMOS, λn and |λp| are generally unequal Similar comments are applicable for VAn and |VAp| Exploring the saturation zone of an enhancement nMOSFET Channel length modulation due to pinch off effect and the dependence of iD on vDS after saturation, are the points which are of concern. Increasing vDS beyond VDSat yields the following modification: The relevant equations depicting the presence of a finite output resistance are: where, λ is the process technology and channel length dependent parameter. λ is inversely proportional to channel length L Hence, r0 (the finite output resistance) is OR The large signal equivalent circuit model incorporating r0 (the finite output resistance) A depletion type n-MOSFET and its characteristic Circuit Symbol: iD-vGS characteristic : It is a type of MOSFET which can be used both in depletion and enhancement operation. The secondary effects 1. Effect on Vt and MOSFET transconductance with increase in temperature. 2. Avalanche breakdown with increase in vDS 3. Breakdown of the gate oxide with increase in vGS 4. Velocity saturation of the carriers with increase in vDS in short channel devices. 5. The body effect or Substrate effect; substrate maintained at a different potential with respect to the source terminal. Determination of the zone of operation while analyzing MOSFET circuits In general, we assume the MOSFET to be in saturation zone of operation (if nothing specific is mentioned regarding conduction of current) , solve the problem or analyze the circuit and then check whether the conditions for saturation mode is satisfied. If there is discrepancy, we consider the triode zone of operation and re-analyze. In this regard, we consider TWO different cases; one is n-channel MOSFET and the other complementary MOSFET. Case 1: n-channel MOSFET GIVEN: Vtn = 1 volt, kn’ (W/L) = 1mA/V2, λ = 0 ANALYSIS: There is no gate current, hence IG = 0 VG = [RG2 / (RG1 + RG2)] × VDD = 5 volts ID being the drain current, VS = 6ID So, VGS = 5 – 6ID volts Assuming, saturation zone operation ID = (1/2) kn’ (W/L) (VGS – Vtn)2 i.e. 18(ID)2 – 25ID + 8 = 0 OR ID = 0.89mA , ID = 0.5mA Feeding ID = 0.89mA makes VS > 5 volts which does not make sense; indicates cut off Hence, ID =0.5mA and VS = 3 volts or VGS = 2 volts Therefore, VD = VDD – 6ID = 7 volts OR VDS = VD – VS = 4 volts The overdrive voltage VOV = VGS - Vtn = 1 volt We observe VDS > VOV , hence the assumption of SATURATION region of operation is correct. Case 2: complementary MOSFET Mode 1 GIVEN: Vtn = |Vtp| = 1 volt, kn’ (Wn/Ln) = kp’ (Wp/Lp) = 1mA/V2 Input voltage application vi = 0,+2.5 volts, -2.5 volts ANALYSIS: In this mode the biasing arrangement is connected to the source terminals of p-channel and n- channel MOSFETs. We need to find the drain current components and the output voltage. Considering vi = 0 volts, both VGS,n-channel & VGS,p-channel are greater than the respective threshold voltages, Vtn & Vtp ; BOTH are in conduction, symmetrical circuit with output voltage, vo = 0 volts Therefore, VDS = 2.5 volts and > VGS - Vt and hence in saturation mode in n-channel MOSFET. Symmetrical comments are applicable for p-channel MOSFET. IDn = IDp = (1/2) × 1 × (2.5 - 1)2 = 1.125mA Considering vi = +2.5 volts, n-channel MOSFET is ON with VGS,n-channel = 5 volts & p- channel MOSFET is OFF with VGS,p-channel = 0 volts Hence, vo = -10IDn volts OR VGD > Vtn indicating operation in the triode or active zone ; assuming small level of VDS IDn = (1/2) × 1 × (5 - 1) × (vo –(-2.5)) Again, IDn = (0-vo)/10 From these equations we get IDn = 0.244mA and vo = -2.44 volts indicating very small value of VDS Considering vi = -2.5 volts, applying symmetrical property, we observe triode zone of operation of ON p-channel MOSFET with VGS,p-channel = -5 volts and OFF n-channel MOSFET with VGS,n-channel = 0 volts Accordingly, IDp = 0.244mA and vo = 2.44 volts Mode 2 GIVEN: Vtn = |Vtp| = 1 volt, kn’ (Wn/Ln) = kp’ (Wp/Lp) = 1mA/V2 Input voltage application vi = 0,+2.5 volts, -2.5 volts ANALYSIS: Here, the drain terminals are connected to the biasing supply, just the opposite. Considering vi = 0 volts, VGS,n-channel = VGS,p-channel = 0 volts indicating both the transistors are in cut off mode or IDn = IDp = 0 mA and vo = 0 volts Considering vi = +2.5 volts, i.e. VGD,n-channel = 0 volts or the n-channel MOSFET is in saturation zone (in conduction phase). This indicates vo or VS is at a lower potential than +2.5 volts or in other words, 0