LDCA Unit 2 Notes PDF
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Uploaded by HottestNash
Noida Institute of Engineering and Technology, Greater Noida
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These notes cover fundamental concepts in computer architecture, focusing on register transfer, micro-operations, and hardware organization. It explains different types of registers, their uses, and how they interact. The notes also discuss topics like addressing modes, stacks, and common bus systems.
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# Register Transfer - DSD uses a **modular approach**.  - **Modules** are best defined by the registers they contain and operations that can be performed on data stored in them. ## Micro-operations - **Operations** performed/executed on data stored in registers.  - **Any elementary oper...
# Register Transfer - DSD uses a **modular approach**.  - **Modules** are best defined by the registers they contain and operations that can be performed on data stored in them. ## Micro-operations - **Operations** performed/executed on data stored in registers.  - **Any elementary operation**.  - The **result** can replace the data's or be stored in other registers. - **Examples:** shift, clear, load. ## Hardware Organization - Therefore, the internal hardware organization of a digital computer is best defined by the **set of registers**, **micro-operations**, and the **control** that initiates the micro-operations. ## Register Transfer Language - **The symbolic notation** needed to describe micro-operations transferred among registers is called **Register Transfer Language**. - **Availability of hardware circuits** (logic circuits) that can perform a stated micro-operation and transfer the results to the same or another register.  ## Registers - Registers are denoted by **Capital letters**. - **Examples:** - **MAR:** Memory address register - **PC:** Program counter - **IR:** Instruction register - **RI:** Register RI - **R2:** 16-bit register R2 <start_of_image> схема: Image of the register RI - **Higher order bits** - **Lower order bits** ## Register Transfers - **R2 ← RI**  - **Copies** contents of register RI to R2. - **Replaces** R2 contents. - **RI contents** do not change. ## Control Condition - Transfer under **predetermined control condition**. - **Example:** If (P=1) then (R2 ← RI) ## Boolean Variable - **Control Function** - **Boolean variable** (0 or 1) - **Scenario:** - Control unit P - Register R2 - Load unit - Clock signal ## Basic Symbols - **Letters** and **numerals** denote a register. - **Parentheses** denote part of a register. - **Arrows** denote transfer of information. - **Commas** separate two operations that are executed at the same time. ## Bus and Memory Transfer - A computer has many registers. - Transfer of data from one register to another needs a path. - Providing separate paths is not possible.  - Therefore, a **common bus system is an efficient scheme for transferring information between registers in a multi-register configuration**. - **Diagram** - **One way** to construct a this is by using MUX. - **MUX** is used to select the source register. - **Explanation** - **4 registers:** A, B, C, D (4-bit each) - **2 common select lines**: So, S1. - **4 MUX:** (4:1M) - **Table** | So S1 | Register Selected | |---|---| | 00 | A | | 01 | B | | 10 | C | | 11 | D | - **In general:** - **K registers** (n-bit each) - **Number of MUX:** n - **MUX configuration:** K:1 - **Transfer:** - **Bus ← C, RI ← BUS** - **RI ← C** ## Three-State Buffers - Instead of MUX, three-state buffers can also be used. - **Digital circuit** that exhibits three states - **Scenario:** - **Normal input:** A - **Control input:** C - **Output:** Y - **Conditions:** - **Y = A if C = 1** - **High if C = 0** - **Open circuit** - **Diagram:** - *n-bit each* - *4 buffers in each* - *n line bus* ## Memory Transfer - Two operations: **Read** and **Write** - **Modules:** - **M:** memory word - **AR:** address register  ## Micro-operations - Arithmetic - **Examples:** - R3 ← RI + R2 - R3 ← RI - R2 - R2 ← R2 - RI ← RI + 1 - RI ← RI -1 - **Hardware** is required to perform any micro-operations. - **Logical** - **Examples:** - P: RI ← RI ⊕ R2 (XOR) - P: RI ← RI V R2 (OR) - P: RI ← RI Λ R2 (AND)  - RI ← SHL RI (Shift Left) - RI ← SHR RI (Shift Right) ## Processor Organisation - **CPU** is a part of a computer that performs the bulk of data processing operations. - **CPU** is made up of three major parts: - **Registers** - **ALU** - **CU** - **Diagram** - **Control** - **Register Set** - **ALU** - **Instructions** - **Instruction Set** - **Instruction Format** - **Addressing Modes**  ## General Register Design - **Diagram** ## Stack Organization - **LIFO:** Last in first out.  - **Stack Pointer:** Register that holds the address for the stack.  - **Insertion** and **deletion:** - **Push** - **Pop** - **Stack:** Portion of memory, collection of registers. - **64 word register stack:** - **Diagram:** - **SP:** stack pointer - **DR:** - **FULL:** - **EMPTY:** - **Values:** 0- 63, 64 - **Initially:** - SP = 0  - EMPTY = 1  - FULL = 0 - **Push:** - **If FULL = 0:** - **SP ← SP + 1** - **M[SP] ← DR**  - **Pop:** - **If SP = 0** then **(FULL ← 1)** - **EMPTY ← 0**  - **DR ← M[SP]** - **SP ← SP - 1**  - **If (SP = 0)** then **EMPTY ← 1, FULL ← 0** - **Example** - **Diagram:** - **PC:** program counter - **AR:** address register - **SP:** stack pointer - **DR:** data register - **Values:** 1000, 2000, 3000, 3997, 4001 - **Stacks for evaluating arithmetic expressions.** - **Notation:**  - **Suffix:** A + B - **Prefix:** + A B - **Postfix:** A B + - **Examples:** - A * B + C * D - A B * C D * + - (3 * 4) + (5 * 6) ## Single Accumulator Organisation ## Instruction Format - **Opcode + operand** - **Scenario:** - **Operand:** X - **Address:** 1 address - **Operation:** ADD (Add), STORE (Store) - **Registers:** ACC - **Operation:** AC ← AC + M[X] - **Scenario:** - **Operands:** R1, R2, R3 - **Address:** 3 addresse - **Operation:** ADD - **Register:** Gen Reg - **Operation: ADD R1, R2, R3** - **Scenario:** - **Operands:** R1, R2 - **Address:** 2 addresses - **Operation:** MOV (Move) - **Operation:** MOV R1, R2 - **Scenario:** - **Operand:** X - **Address:** 1 address - **Operation:** ADD - **Operation:** ADD R1, X - **Scenario:** - **Operand:** X - **Address:** 1 address - **Operation:** PUSH - **Operation:** PUSH X - **Scenario:** - **Operand:** none - **Address:** 0 addresses - **Operation:** ADD - **Operation:** ADD - **Example:** - **X = (A + B) * (C + D)** - **Operations:** - ADD R1, A, B - MOV R1, A - ADD R2, C, D - ADD R1, B - MUL X, R1, R2 - MOV R2, C - ADD R2, D - LOAD A - ADD B - STORE T - LOAD C - MUL R1, R2 - ADD D - MULT - STORE X - PUSH A - PUSH B - ADD - PUSH C - PUSH D - ADD - MUL - POP ## Addressing Modes - **The way operands are chosen.** - **Rule for interpreting and modifying** the address field of the instruction. - **Fetch-Decode-Execute cycle** 1. **Implied Mode:** - **Operands** are specified implicitly in the definition of the instruction. - **Opcode** itself specifies the operand. - **Examples:** - CMA - INR - PUSH - POP 2. **Immediate Mode:** - **Operands** are specified in the instruction itself.  - **Examples:** - ADD A, 05 - ADD 05 3. **Register Mode:** - **Registers** are used. - **Examples:** - ADD R1, R2 4. **Register Indirect Mode:** - **Instruction specifies a register** whose contents give the address of the operand in the memory. - **Example:** - Add R1, M[AR] 5. **Direct Address Mode:** - **The operand resides in memory** and its address is given directly in the instruction. - **Example:** - LOAD. 20504.  6. **Indirect Address Mode:** - **Address field gives an address** where the effective address is stored in memory/register. - **Example:** - Load M[AR]. 7. **Relative Addressing Mode:** - **Effective Address = Address part of the instruction + contents of the PC register** 8. **Indexed Addressing Mode:** 9. **Base Register Addressing Mode:**
